MC68HC08AS20 Datasheet, PDF (219/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

16.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE:
If TCNTH is read during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Register Name and Address TCNTH — $0022
Bit 7
6
5
4
3
2
1
Bit 0
Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
Write:
Reset: 0
0
0
0
0
0
0
0
Register Name and Address TCNTL — $0023
Bit 7
6
5
4
3
2
1
Bit 0
Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-4. TIM Counter Registers (TCNTH and TCNTL)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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