MC68HC08AS20 Datasheet, PDF (121/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

9.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 9-2. This clock can come
from either an external oscillator or from the on-chip PLL. (See Section
8. Clock Generator Module (CGM).)
9.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See Section 8. Clock Generator Module (CGM).)
9.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
OSC1
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
Figure 9-2. CGM Clock Signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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