MC68HC08AS20 Datasheet, PDF (181/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

15.3.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
Address: $0004
Bit 7
Read:
DDRA7
Write:
Reset:
6
DDRA6
5
DDRA5
4
3
DDRA4 DDRA3
Unaffected by Reset
2
DDRA2
1
DDRA1
Figure 15-2. Data Direction Register A (DDRA)
Bit 0
DDRA0
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 15-3 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAx
READ PTA ($0000)
Figure 15-3. Port A I/O Circuit
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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