MC68HC08AS20 Datasheet, PDF (187/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

15.5.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer for
the corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006
Bit 7
6
5
Read:
0
0
MCLKEN
Write:
Reset: 0
0
0
= Unimplemented
4
3
2
1
Bit 0
DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
0
0
0
0
0
Figure 15-8. Data Direction Register C (DDRC)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, PTC2 is under the control of MCLKEN. Reset
clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[4:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 15-9 shows the port C I/O logic.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
187