CS43130 Datasheet, PDF (99/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
7.2 PLL Registers
7.2.6 PLL Setting 6
R/W
7
6
5
4
3
2
PLL_OUT_DIV
Default
0
0
0
1
0
0
Bits
Name
7:0 PLL_OUT_ Final PLL clock output divide value.
DIV
0001 0000 (Default)
Description
Address 0x30008
1
0
0
0
7.2.7 PLL Setting 7
Address 0x3000A
R/W
7
6
5
4
3
2
1
0
PLL_CAL_RATIO
Default
1
0
0
0
0
0
0
0
Bits
Name
Description
7:0 PLL_CAL_ PLL calibration ratio. See Section 4.7.2 for configuration details. Target value for PLL VCO calibration.
RATIO
1000 0000 (Default)
7.2.8 PLL Setting 8
Address 0x3001B
R/W
7
6
5
4
3
2
1
0
—
PLL_MODE
—
Default
0
0
0
1
0
0
1
1
Bits
Name
Description
7:2
—
Reserved
1 PLL_MODE 500/512 factor used in PLL frequency calculation equation, Eq. 4-1.
0 No bypass
1 (Default) Bypass
0
—
Reserved
7.2.9 PLL Setting 9
R/W
7
6
5
4
3
2
—
Default
0
0
0
0
0
0
Bits
Name
7:2
—
Reserved
1:0 PLL_REF_ PLL reference divide select.
PREDIV
00 Divide by 1
01 Divide by 2
10 (Default) Divide by 4
11 Divide by 8
Description
Address 0x40002
1
0
PLL_REF_PREDIV
1
0
DS1073F1
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