CS43130 Datasheet, PDF (104/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
7.3 ASP and XSP Registers
7.3.18 XSP LRCK Period 1
R/W
7
6
5
4
3
2
XSP_LCPR_LSB
Default
0
0
1
1
1
1
Bits
Name
Description
7:0 XSP_LCPR_ The value in this register cannot be changed while the serial port is powered up.
LSB
XSP LRCK period, in units of XSP_SCLK periods stored in XSP_LCPR_LSB/MSB.
(Default) XSP_LCPR = 63
Address 0x40026
1
0
1
1
7.3.19 XSP LRCK Period 2
R/W
7
6
5
4
3
2
XSP_LCPR_MSB
Default
0
0
0
0
0
0
Bits
Name
Description
7:0 XSP_LCPR_ The value in this register cannot be changed while the serial port is powered up.
MSB
XSP LRCK period, in units of XSP_SCLK periods stored in XSP_LCPR_LSB/MSB.
(Default) XSP_LCPR = 63
Address 0x40027
1
0
0
0
7.3.20
R/W
Default
XSP Clock Configuration
7
6
5
—
0
0
0
4
XSP_M/SB
0
Address 0x40028
3
XSP_SCPOL_
OUT
1
2
XSP_SCPOL_
IN
1
1
XSP_LCPOL_
OUT
0
0
XSP_LCPOL_
IN
0
Bits
Name
7:5
—
Reserved
4 XSP_M/SB XSP port master or slave configuration.
0 (Default) Slave Mode (input)
1 Master Mode (output)
3 XSP_SCPOL_ XSP SCLK output drive polarity.
OUT
0 Normal
1 (Default) Inverted
2 XSP_SCPOL_ XSP SCLK input polarity (pad to logic).
IN
0 Normal
1 (Default) Inverted
1 XSP_LCPOL_ XSP LRCK output drive polarity.
OUT
0 (Default) Normal
1 Inverted
0 XSP_LCPOL_ XSP LRCK input polarity (pad to logic).
IN
0 (Default) Normal
1 Inverted
Description
7.3.21 XSP Frame Configuration
Address 0x40029
R/W
7
6
5
4
3
2
1
0
—
XSP_STP
XSP_5050
XSP_FSD
Default
0
0
0
0
1
0
1
0
Bits
Name
Description
7:5
—
Reserved
4 XSP_STP XSP start phase. Controls which LRCK/FSYNC phase starts a frame.
0 (Default) The frame begins when LRCK/FSYNC transitions from high to low
1 The frame begins when LRCK/FSYNC transitions from low to high
3 XSP_5050 XSP LRCK fixed 50/50 duty cycle.
0 Programmable duty cycle per XSP_LCHI and XSP_LCPR
1 (Default) Fixed 50% duty cycle
104
DS1073F1