CS43130 Datasheet, PDF (48/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.9 Audio Serial Port (ASP)
• If xSP_STP = 0, the frame begins when LRCK/FSYNC transitions from high to low. See Fig. 4-26 for an example
in 50/50 mode. The TDM Mode behaves similarly.
...
LRCK xSP_STP = 0
...
SCLK
...
...
Channel location index
(xSP_CHy_LOC ,
xSP_CHz_LOC)
Previous
Sample
012
...
N/2 N/2 N/2
-3 -2 -1
0
1
2
...
N/ 2 N/2 N/2
-3 -2 -1
Channel y
Channel z
Next
Sample
SDIN
xSP_CHy_LOC = 0,
xSP_CHy_AP = 0
xSP_CHz_LOC = 0,
xSP_CHz_AP = 1
Note: This diagram assumes xSP _FSD = 0.
Figure 4-26. Example 50/50 Mode (ASP_STP = 0)
• If xSP_STP = 1, the frame begins when LRCK/FSYNC transitions from low to high. See Fig. 4-27 for an example
in 50/50 mode. TDM mode is similar.
...
LRCK xSP_STP = 1
...
SCLK
...
...
Channel location index
(xSP_CHy_LOC ,
xSP_ CHz_ LOC)
Previous
Sample
012
...
N/2 N/2 N/2
-3 -2 -1
0
1
2
...
N/2 N/2 N/2
-3 -2 -1
Channel z
Channel y
Next
Sample
SDIN
xSP_CHz_LOC = 0,
xSP_CHz_AP = 1
Note: This diagram assumes xSP_ FSD = 0.
xSP_CHy_LOC = 0,
xSP_CHy_AP = 0
Figure 4-27. Example 50/50 Mode (ASP_STP = 1)
4.9.8 50/50 Mode
In typical two-channel I²S operation (50/50 Mode, xSP_5050 = 1), the LRCK duty cycle is 50%, and each channel is
transferred during one of the two LRCK phases. In this mode, each serial port channel can be independently programmed
to output when LRCK/FSYNC is high or low; this is called the channel-active phase.
If the active-phase control bit (xSP_RX_CHn_AP) is set, the respective channel is output when LRCK/FSYNC is high. If
xSP_RX_CHn_AP is cleared, the respective channel is output if LRCK/FSYNC is low. Examples of each setting of xSP_
RX_CHn_AP are shown in Fig. 4-26 and Fig. 4-27.
In 50/50 Mode, the channel location (see Section 4.9.6) is calculated within the channel-active phase. If there are N bits
in a frame, the location of the last bit of each active phase is equal to (N/2) – 1.
Note: If xSP_5050 is set, xSP_LCHI must be programmed to half of xSP_LCPR for a 50% duty cycle. Also, only two
channels can be enabled for the corresponding serial port.
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DS1073F1