CS43130 Datasheet, PDF (42/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.9 Audio Serial Port (ASP)
The combination of the options results in five different filter combinations. The specifications for each filter can be found
in Table 3-8, and response plots can be found in Section 9. These filters have been designed to accommodate a variety
of musical tastes and styles. The PCM filter option register (see Section 7.5.2) is used to select filter options.
When in octuple-speed mode, the filter options above are not available and the internal digital processing is minimized.
See the specification in Table 3-8 for filter characteristics.
The DSD processor mode uses a decimation-free DSD processing technique that allows for features such as matched
PCM level output, DSD volume control, and 50-kHz on-chip filter.
4.9 Audio Serial Port (ASP)
The independent, highly configurable ASPs and auxiliary serial ports (XSPs) communicate audio data from other system
devices, such as applications processors. Both ports can be configured to support common audio interfaces, TDM/I²S and
left-justified (LJ).
ASP supports both PCM and DoP stream playback. XSP can only support DoP stream playback. For DAC playback, only
one port needs to be enabled. Both ports are enabled only in specific application, such as PCM notification mixing with
DSD/DoP content. Details regarding this application setup can be found in Section 4.12.
In this section, the reference to both ports is generalized as “xSP” to explain the common settings between the two ports.
4.9.1 Master and Slave Timing
Each serial port can operate as either the master of timing or as a slave to another device’s timing. If xSP_M/S is set, the
serial port acts as a clock master. If xSP_M/S is cleared, the serial port acts as a clock slave.
• In Master Mode, xSP_SCLK and xSP_LRCK are outputs derived from the internal MCLK.
• In Slave Mode, xSP_SCLK and xSP_LRCK are inputs. Although the CS43130 does not generate the interface
timings in Slave Mode, the expected LRCK and SCLK format must be programmed in the same way as in Master
Mode (see Table 3-18).
• In both modes, the serial port sample rate register (xSP_SPRATE) must be set per audio content before enabling
the serial port.
• When using ASP for PCM playback, the audio serial port sample bit size register (ASP_SPSIZE) must be set per
audio content before enabling the ASP.
• When using XSP or ASP for DoP playback, the serial port sample bit size register (XSP_SPSIZE or ASP_SPSIZE)
must be set per audio content before enabling the XSP or ASP. Note that the XSP_SPSIZE or ASP_SPSIZE must
reflect the length of both DSD marker bits together with audio bits.
4.9.2 Power-Up, Power-Down, and Tristate
The xSP has separate power-down and tristate controls (PDN_xSP and xSP_3ST) for input data paths, which minimizes
power consumption if the input port is not used. xSP master/slave operation is controlled only by the xSP_M/S setting,
irrespective of the PDN_xSP and xSP_3ST settings.
• PDN_xSP. If a serial port’s SDIN functionality is not required, xSP can be powered down by setting PDN_xSP,
which powers down the input data path and clocks of the serial port.
• xSP_3ST. In Master Mode, setting xSP_3ST tri-states the SCLK and LRCK clocks. Before setting an xSP_3ST bit,
the associated serial port must be powered down and must not be powered up until the xSP_3ST bit is cleared. In
Slave Mode, xSP_3ST does not affect the functionality of SCLK and LRCK clocks, given both pins are input pins.
4.9.3 I/O
The ASP port is associated with SDIN1, SCLK1, and LRCK1. The XSP port is associated with SDIN2, SCLK2, and LRCK2,
which are shared with DSD interface:
• SCLKx—Serial data shift clock
42
DS1073F1