CS43130 Datasheet, PDF (108/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
7.4 DSD Registers
7.4.5
R/W
Default
DSD Processor Path Signal Control 2
7
6
5
4
—
DSD_PRC_SRC
DSD_EN
0
0
0
0
Address 0x70004
3
2
1
0
—
DSD_SPEED STA_DSD_DET INV_DSD_DET
0
0
1
0
Bits
Name
Description
7
—
Reserved
6:5 DSD_PRC_ Select the source for DSD processor.
SRC
00 (Default) DSD interface
01 Reserved
10 ASP
11 XSP
4
DSD_EN Enable DSD playback.
0 (Default) Function disabled
1 DSD playback is enabled
3
—
Reserved
2 DSD_SPEED Setup DSD clock speed.
0 (Default) 64•Fs
1 128•Fs
1 STA_DSD_ Static DSD detection.
DET
0 Function disabled
1 (Default) Static DSD detection is enabled. The DSD processor checks for 28 consecutive zeros or ones and, if
detected, sets the DSD_STUCK_INT interrupt status bit and mutes the output until the static condition is cleared.
0 INV_DSD_ Invalid DSD detection.
DET
0 (Default) Function disabled
1 Invalid DSD detection is enabled. The DSD processor checks for 25 out of 28 bits of the same value and, if
detected, sets the DSD_INVAL_A_INT and/or DSD_INVAL_B_INT interrupt status bits.
7.4.6 DSD and PCM Mixing Control
Address 0x70005
R/W
7
6
5
4
3
2
1
0
—
MIX_PCM_
PREP
MIX_PCM_
DSD
Default
0
0
0
0
0
0
0
0
Bits
Name
Description
7:2
—
Reserved
1 MIX_PCM_ Enable PCM playback path for PCM and DSD mixing. This bit must be set prior to setting MIX_PCM_DSD. Disable this
PREP bit after disabling MIX_PCM_DSD. This mode requires DSD_EN to be enabled and DSD_PRC_SRC set to receive DSD
through either the DSD interface or XSP.
0 (Default) Function disabled
1 Enable PCM playback path for PCM and DSD mixing
0 MIX_PCM_ Enable PCM stream mixing into DSD stream. This bit must be set only after MIX_PCM_PREP is enabled. Disable this
DSD
bit prior to disabling MIX_PCM_PREP bit. This mode requires DSD_EN to be enabled and DSD_PRC_SRC set to
receive DSD through either the DSD interface or XSP.
0 (Default) Function disabled
1 Enable PCM stream mixing into the DSD stream
7.4.7 DSD Processor Path Signal Control 3
R/W
7
6
5
DSD_ZERODB DSD_HPF_EN
—
4
SIGCTL_
DSDEQPCM
Default
0
1
0
0
3
DSD_INV_A
0
Address 0x70006
2
DSD_INV_B
0
1
DSD_SWAP_
CHAN
0
0
DSD_COPY_
CHAN
0
Bits
Name
Description
7
DSD_ Setting on DSD stream volume to match PCM stream volume.
ZERODB
0 (Default) The SACD +3.1-dB level (71% modulation index) matches PCM 0 dB full scale.
1 The SACD 0-dB reference level (50% modulation index) matches PCM 0 dB full scale.
6 DSD_HPF_EN Enable the high pass filter in the DSD processor.
0 HPF disabled
1 (Default) Enable HPF in the DSD processor
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DS1073F1