CS43130 Datasheet, PDF (107/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
7.4 DSD Registers
7.4.2 DSD Volume A
R/W
7
6
5
4
3
2
DSD_VOLUME_A
Default
0
1
1
1
1
0
Bits
Name
Description
7:0
DSD_ Digital volume control registers for channel A. See DSD_VOLUME_B for description.
VOLUME_A
Address 0x70001
1
0
0
0
7.4.3
R/W
Default
DSD Processor Path Signal Control 1
7
6
5
4
—
DSD_VOL_
BEQA
DSD_SZC
—
1
0
1
0
Address 0x70002
3
DSD_AMUTE
1
2
1
0
DSD_AMUTE_
BEQA
DSD_MUTE_A
DSD_MUTE_B
0
0
0
Bits
Name
Description
7
—
Reserved
6 DSD_VOL_ DSD_VOLUME_B equals DSD_VOLUME_A.
BEQA
0 (Default) Volume setting of both channels in DSD processor are controlled independently
1 Volume setting of both channels are controlled by DSD_VOLUME_A. DSD_VOLUME_B is ignored
5 DSD_SZC Soft ramp control.
0 Immediate change
1 (Default) Soft ramp
4
—
Reserved
3 DSD_AMUTE DSD auto mute.
0 Function disabled
1 (Default) Mute occurs after reception of 256 repeated 8-bit DSD mute patterns. A single bit not fitting the repeated
pattern releases the mute. Detection and muting is done independently for each channel.
2
DSD_ DSD Processor Auto mute channel B equals channel A.
AMUTE_
0 (Default) Function disabled
BEQA
1 Only mute when both channels AMUTE conditions are detected
1 DSD_MUTE_ DSD Processor Channel A mute.
A
0 (Default) Function is disabled
1 Channel output is muted. Muting function is affected by the DSD_SZC bit
0 DSD_MUTE_ DSD Processor Channel B mute.
B
0 (Default) Function is disabled.
1 Channel output is muted. Muting function is affected by the DSD_SZC bit.
7.4.4 DSD Interface Configuration
R/W
7
6
5
4
—
Default
0
0
0
0
Address 0x70003
3
2
1
0
DSD_M/SB DSD_PM_EN DSD_PM_SEL
0
0
0
0
Bits
Name
Description
7:3
—
Reserved
2 DSD_M/SB DSD clock master or Slave Mode.
0 (Default) Slave Mode
1 Master Mode
1 DSD_PM_EN DSD phase modulation mode. Can only be used when DSD_SPEED = 0 (64•Fs).
0 (Default) this function is disabled (DSD normal mode)
1 DSD phase modulation input mode is enabled, and the DSD_PM_SEL bit must be set accordingly.
0 DSD_PM_SEL DSD phase modulation mode select.
0 (Default) The 128•Fs (BCKA) clock must be input to DSD_SCLK for phase modulation mode.
1 The 64•Fs (BCKD) clock must be input to DSD_SCLK for phase modulation mode.
DS1073F1
107