CS43130 Datasheet, PDF (51/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.10 DSD Interface
• Sourcing MCLK_INT and DSDCLK from the same external clock source
The DSD_EN bit, when set, is used to configure the device for processing DSD sources. DSD_PRC_SRC configures the
DSD interface used for feeding into the DSD processor. DSD_SPEED specifies if a 64•Fs or 128•Fs DSD stream is
provided. If PDN_DSDIF = 0 and DSD_M/SB = 1, DSD_SPEED determines the DSDCLK clock frequency generated.
When configuring the DSD interface, follow these steps:
1. Configure the DSD_M/SB, DSD_SPEED, DSD_PRC_SRC, and XSP_3ST.
2. Release PDN_DSDIF.
3. Enable DSD_EN.
The DSD_PM_EN bit selects phase modulation (data plus data inverted) as the style of data input. In this mode, the DSD_
PM_SEL bit selects whether a 128•Fs or 64•Fs clock is used for phase-modulated 64•Fs data (see Fig. 4-29). Use of
phase modulation mode may not directly affect the performance of the CS43130, but may lower the sensitivity of other
board-level components to the DSD data signals. Note that phase modulation mode is supported only for DSD 64•Fs data
rate.
The CS43130 can detect overmodulation errors in the DSD data that do not comply to the SACD specification. Setting
INV_DSD_DET enables detection of overmodulation errors. This condition is reported through the DSD_INVAL_A_INT
and DSD_INVAL_B_INT status bits. Overmodulated DSD data is converted as received without intervention, but
performance at these levels cannot be guaranteed. Setting STA_DSD_DET allows the CS43130 to mute a DSD stream
that is stuck at 1 or 0. This condition is reported through the DSD_STUCK_INT status bit. See Section 7.6.5 for
descriptions of the DSD error reporting bits.
More information for these register bits can be found in Section 7.
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index) at
full-rated performance. When 0 dB-SACD and 0 dBFS PCM need to be level matched, DSD_ZERODB must be set. In this
mode, signals of +3-dB SACD may be applied for brief periods of time; however, performance at these levels is not
guaranteed. If sustained levels approaching +3-dB SACD levels are required, DSD_ZERODB must be cleared, which
matches a +3-dB SACD output level.
DSD Normal Mode
(DSD_PM_EN = 0)
DSDCLK
(64•Fs or
128•Fs)
DSDA ,
DSDB
D0
D1
D2
DSD Phase
Modulation Mode
(DSD_PM_EN = 1)
DSDCLK (128•Fs)
(DSD_PM_SEL = 0)
DSDCLK (64•Fs)
(DSD_PM_SEL = 1)
DSDA ,
DSDB
D0
D1
D1
D2
Figure 4-29. DSD Phase Modulation Mode Diagram
DS1073F1
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