CS43130 Datasheet, PDF (79/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
Example 5-19. DoP and PCM Mixing (Cont.)
STEP
TASK
28 Headphone Detect
REGISTER/BIT FIELDS
HP Detect. 0xD0000
VALUE
0xC4
DESCRIPTION
HPDETECT_CTRL
HPDETECT_INV
HPDETECT_RISE_DBC_TIME
HPDETECT_FALL_DBC_TIME
Reserved
11 HP Detect enabled
0 HP detect input is not inverted
00 Tip Sense rising debounce time set to 0 ms
10 Tip sense falling debounce time set to 500 ms
0
29 Enable Interrupts
30 Read Interrupt Status 1 register (0xF0000), Interrupt Status 2 register (0xF0001) and Interrupt Status 5 register (0xF0004) to clear sticky bits
31 Enable Headphone Detect
Interrupts
Interrupt Mask 1. 0xF0010
DAC_OVFL_INT_MASK
HPDETECT_PLUG_INT_MASK
HPDETECT_UNPLUG_INT_MASK
XTAL_READY_INT_MASK
XTAL_ERROR_INT_MASK
PLL_READY_INT_MASK
PLL_ERROR_INT_MASK
PDN_DONE_INT_MASK
0x99
1
0
0
1
1
0
0
1
DAC_OVFL_INT is don’t care
Unmask HPDETECT_PLUG interrupt
Unmask HPDETECT_UNPLUG interrupt
XTAL_READY_INT is don’t care
XTAL_ERROR_INT is don’t care
PLL_READY Interrupt is already unmasked
PLL_ERROR Interrupt is already unmasked
PDN_DONE_INT is don’t care
32 Enable XSP Interrupts
Interrupt Mask 2. 0xF0011
0x07
XSP_OVFL_INT_MASK
XSP_ERROR_INT_MASK
XSP_LATE_INT_MASK
XSP_EARLY_INT_MASK
XSP_NOLRCK_INT_MASK
Reserved
0 Enable XSP_OVFL interrupt
0 Enable XSP_ERROR interrupt
0 Enable XSP_LATE interrupt
0 Enable XSP_EARLY interrupt
0 Enable XSP_NOLRCK interrupt
111
33 Enable DSD and DoP
Interrupts
Interrupt Mask 5. 0xF0014
DSD_STUCK_INT_MASK
DSD_INVAL_A_INT_MASK
DSD_INVAL_B_INT_MASK
DSD_SILENCE_A_INT_MASK
DSD_SILENCE_B_INT_MASK
DSD_RATE_ERROR_INT_MASK
DOP_MRK_DET_INT_MASK
DOP_ON_INT_MASK
0x01
0
0
0
0
0
0
0
1
Enable DSD_STUCK interrupt
Enable DSD_INVAL_A interrupt
Enable DSD_INVAL_B interrupt
Enable DSD_SILENCE_A interrupt
Enable DSD_SILENCE_B interrupt
Enable DSD_RATE_ERROR interrupt
Enable DOP_MRK_DET interrupt
Disable DOP_ON interrupt
34 Set MCLK Source and
Frequency
System Clocking Control. 0x10006
Reserved
MCLK_INT
MCLK_SRC_SEL
0x04
0000 0
1 MCLK Frequency is set to 22.5792 MHz
00 MCLK Source is set to XTAL
35 Wait for at least 150 µs
36 Enable XSP Clocks
Pad Interface Configuration. 0x1000D 0x01
Reserved
XSP_3ST
ASP_3ST
0000 00
0 ASP Interface status is don’t care (set to default)
1 Enable XSP serial clocks in master mode
37 Apply DSD Power-up Sequence in Ex. 5-10. Note that in Step 2 of Ex. 5-10, HH = 7F for DoP on XSP interface. Skip Step 1 of Ex. 5-10 (completed
in Step 7 above).
38 Enable ASP
39 Set ASP sample rate
Serial Port Sample Rate. 0x1000B
0x01
Reserved
ASP_SPRATE
0000
0001 Set sample rate to 44.1 kHz
40 Set ASP sample bit size
Serial Port Sample Bit Size. 0x1000C 0x04
Reserved
XSP_SPSIZE
ASP_SPSIZE
0000
01
00 ASP sample bit size set to 32 bits
41 Set ASP Numerator
ASP Numerator 1. 0x40010
0x01
ASP_N_LSB
0x01 LSB of ASP sample rate fractional divide numerator
ASP Numerator 2. 0x40011
0x00
ASP_N_MSB
0x00 MSB of ASP sample rate fractional divide numerator
42 Set ASP Denominator
ASP Denominator 1. 0x40012
0x08
ASP_M_LSB
0x08 LSB of ASP sample rate fractional divide denominator
ASP Denominator 2. 0x40013
0x00
ASP_M_MSB
0x00 MSB of ASP sample rate fractional divide denominator
43 Set ASP LRCK high Time ASP LRCK High Time 1. 0x40014
0x1F
ASP_LCHI_LSB
0x1F LSB of ASP LRCK high time duration
ASP LRCK High Time 2. 0x40015
0x00
ASP_LCHI_MSB
0x00 MSB of ASP LRCK high time duration
44 Set ASP LRCK period
ASP LRCK Period 1. 0x40016
0x3F
ASP_LCPR_LSB
0x3F LSB of ASP LRCK period
ASP LRCK Period 2. 0x40017
0x00
ASP_LCPR_MSB
0x00 MSB of ASP LRCK period
DS1073F1
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