CS43130 Datasheet, PDF (77/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
Example 5-18. Sequence for Headphone Detection (Cont.)
STEP
TASK
REGISTER/BIT FIELDS
VALUE
DESCRIPTION
6 Wait for interrupt. Check if HPDETECT_PLUG_INT or HPDETECT_UNPLUG_INT is set in the Interrupt Status 1 register (0xF0000).
5.10.9 DoP and PCM Mixing
Ex. 5-19 shows steps necessary to mix DoP and PCM. The XSP is in clock master receiving DoP data with LRCLK at
176.4 kHz and SCLK at 8.4672 MHz. The ASP is clock master receiving PCM data with LRCLK at 44.1 kHz and SCLK at
2.8224 MHz.
Example 5-19. DoP and PCM Mixing
STEP
TASK
REGISTER/BIT FIELDS
1 _{Apply all relevant power supplies, then assert RESET.}
2 Wait for 1.5 ms
3 Configure XTAL Driver
4 Configure XTAL bias current Crystal Setting. 0x20052
strength (assuming River
Crystal at 22.5792 MHz)
Reserved
XTAL_IBIAS
5 Enable XTAL interrupts
Interrupt Mask 1. 0xF0010
DAC_OVFL_INT_MASK
HPDETECT_PLUG_INT_MASK
HPDETECT_UNPLUG_INT_MASK
XTAL_READY_INT_MASK
XTAL_ERROR_INT_MASK
PLL_READY_INT_MASK
PLL_ERROR_INT_MASK
PDN_DONE_INT_MASK
6 Start XTAL
Power Down Control. 0x20000
PDN_XSP
PDN_XSP
PDN_DSDIF
PDN_HP
PDN_XTAL
PDN_PLL
PDN_CLKOUT
Reserved
7 Apply DSD power-up initialization in Ex. 5-8
8 Playback DoP audio. Assuming 64•Fs DSD stream
9 Configure XSP interface for DoP input.
10 Set sample bit size.
Serial Port Sample Bit Size. 0x1000C
Reserved
XSP_SPSIZE
ASP_SPSIZE
11 Set XSP Numerator
XSP Numerator 1. 0x40020
XSP_N_LSB
XSP Numerator 2. 0x40021
XSP_N_MSB
12 Set XSP Denominator
XSP Denominator 1. 0x40022
XSP_M_LSB
XSP Denominator 2. 0x40023
XSP_M_MSB
13 Set XSP LRCK high Time XSP LRCK High Time 1. 0x40024
XSP_LCHI_LSB
XSP LRCK High Time 2. 0x40025
XSP_LCHI_MSB
14 Set XSP LRCK period
XSP LRCK Period 1. 0x40026
XSP_LCPR_LSB
XSP LRCK Period 2. 0x40027
XSP_LCPR_MSB
15 Configure XSP Clock
XSP Clock Configuration. 0x40028
Reserved
XSP_M/SB
XSP_SCPOL_OUT
XSP_SCPOL_IN
XSP_LCPOL_OUT
XSP_LCPOL_IN
VALUE
0x04
0000 0
100
0xE7
1
1
1
0
0
1
1
1
0xF6
1
1
1
1
0
1
1
0
0x05
0000
01
01
0x03
0x03
0x00
0x00
0x08
0x08
0x00
0x00
0x17
0x17
0x00
0x00
0x2F
0x2F
0x00
0x00
0x1C
000
1
1
1
0
0
DESCRIPTION
Bias current set to 12.5 µA
Enable XTAL_READY interrupt
Enable XTAL_ERROR interrupt
Power up XTAL driver
XSP sample bit size is set to 24 bits
ASP sample bit size is set to 24 bits
LSB of XSP sample rate fractional divide numerator
MSB of XSP sample rate fractional divide numerator
LSB of XSP sample rate fractional divide denominator
MSB of XSP sample rate fractional divide denominator
LSB of XSP LRCK high time duration
MSB of XSP LRCK high time duration
LSB of XSP LRCK period
MSB of XSP LRCK period
Set XSP port to be Master
Set output SCLK polarity
Input SCLK polarity is don’t care
Set Output LRCLK polarity
Input LRCLK polarity is don’t care
DS1073F1
77