CS43130 Datasheet, PDF (97/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
7.1 Global Registers
Bits
Name
Description
1 XSP_3ST Determines the state of the XSP clock drivers when in Master Mode. When in Slave Mode, the serial port clocks are
inputs, whose function is not affected by this bit. Before setting an xSP_3ST bit, the associated serial port must be
powered down and not powered up until the xSP_3ST bit is cleared.
0 When in Master Mode, serial port clocks are active.
1 (Default) When in Master Mode, serial port clocks are Hi-Z.
0 ASP_3ST Determines the state of the ASP clock drivers when in Master Mode. When in Slave Mode, the serial port clock pins are
inputs, whose function is not affected by this bit. Before setting an xSP_3ST bit, the associated serial port must be
powered down and not powered up until the xSP_3ST bit is cleared.
0 When in Master Mode, serial port clocks are active.
1 (Default) When in Master Mode, serial port clocks are Hi-Z.
7.1.10 Power Down Control
R/W
7
PDN_XSP
6
PDN_ASP
5
PDN_DSDIF
Default
1
1
1
4
PDN_HP
1
3
PDN_XTAL
1
2
PDN_PLL
1
Address 0x20000
1
0
PDN_CLKOUT
—
1
0
Bits
Name
Description
7 PDN_XSP XSP input path power control. Configures XSP SDIN path power state.
0 Powered up.
1 (Default) Powered down.
6 PDN_ASP ASP input path power control. Configures ASP SDIN path power state.
0 Powered up.
1 (Default) Powered down.
5 PDN_DSDIF DSD interface power control. Sets the power state of the DSD interface block.
0 Powered up.
1 (Default) Powered down.
4
PDN_HP Power down HPOUTx.
0 Powered up. The HP driver and DACx are powered up.
1 (Default) Powered down. The HP driver and DACx are powered down. When this bit is set, the audio outputs are
soft ramped to mute.
3 PDN_XTAL Power down crystal oscillator.
0 Powered up. The XTAL driver is powered up to start generating MCLK.
1 (Default) Powered down. The XTAL driver is powered down.
2 PDN_PLL _{PLL output power control. Sets the power state of the PLL block.}
0 Powered up.
1 (Default) Powered down. PLL block is powered down.
1
PDN_ CLKOUT output power control. Sets the power state of the CLOCKOUT output.
CLKOUT
0 Powered up
1 (Default) Powered down. CLKOUT are driven low.
0
—
Reserved
7.1.11 Crystal Setting
Address 0x20052
R/W
7
6
5
4
3
2
1
0
—
XTAL_IBIAS
Default
0
0
0
0
0
1
0
0
Bits
Name
7:3
—
Reserved
2:0 XTAL_IBIAS Crystal bias current strength.
010 15.0 µA
100 (Default) 12.5 µA
110 7.5 µA
Others Reserved
Description
DS1073F1
97