CS43130 Datasheet, PDF (49/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.9 Audio Serial Port (ASP)
4.9.9 Serial Port Status
Each serial port has five status bits. Each bit is sticky and must be read to be cleared. The status bits have associated
mask bits to mask setting the INT pin when the status bit sets. A brief description of each status bit is shown in Table 4-8.
Table 4-8. Serial Port Status
Name
Request Overload
LRCK Early
LRCK Late
LRCK Error
Description
Set when too many input buffers request processing at the same time. If all channel size
and location registers are properly configured to non-overlapping values, this error
status must never set.
Set when the number of SCLK periods per LRCK phase (high or low) is less than the
expected count as determined by xSP_LCPR and xSP_LCHI.
Note: The Rx LRCK early interrupt status is set during the first receive LRCK early
event. Subsequent receive LRCK early events are not indicated until after valid LRCK
transitions are detected.
Set when the number of SCLK periods per LRCK phase (high or low) is greater than the
expected count as determined by xSP_LCPR and xSP_LCHI.
Logical OR of LRCK early and LRCK late.
No LRCK
Set when the number of SCLK periods counted exceeds twice the value of LRCK period
(xSP_LCPR) without an LRCK edge.
The Tx No LRCK interrupt status is set during the first instance of a no transmit LRCK
condition. Subsequent no transmit LRCK conditions are not indicated until after valid
LRCK transitions are detected.
Register Reference
ASP_OVFL_INT p. 115
XSP_OVFL_INT p. 116
ASP_EARLY_INT p. 116
XSP_EARLY_INT p. 116
ASP_LATE_INT p. 116
XSP_LATE_INT p. 116
ASP_ERROR_INT p. 116
XSP_ERROR_INT p. 116
ASP_NOLRCK_INT p. 116
XSP_NOLRCK_INT p. 116
4.9.10 Serial Port Clock Pin Status
There are various control bits available that affect the output state of the serial port clock and data pins. Table 4-9
summarizes the possible states depending on these bit settings.
Table 4-9. xSP_SCLK and xSP_LRCK/FSYNC Pin States
xSP_3ST
1
0
0
0
xSP_M/S
x
0
1
1
PDN_xSP
x
x
0
1
xSP_SCLK
Pin State
Hi-Z with weak pull-down
Hi-Z with weak pull-down
Active
Inactive
xSP_LRCK/FSYNC
Pin State
Hi-Z with weak pull-down
Hi-Z with weak pull-down
Active
Inactive ¹
1.If xSP_LCPOL_OUT is set, xSP_LRCK/FSYNC inactive output is high. If xSP_LCPOL_OUT is cleared, xSP_LRCK/FSYNC
inactive output is low.
4.9.11 DoP (DSD over PCM) Mode
DoP is a protocol for packetizing DSD data into a PCM frame for transmission over an existing I²S interface. The ASP or
XSP can accept DSD data in DoP format.
To use the DoP interface in Slave Mode, if MCLK_INT = 22.5792 MHz, the DoP interface clocks are required to be
synchronous to MCLK_INT.
DS1073F1
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