CS43130 Datasheet, PDF (22/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
3 Characteristics and Specifications
3.I²S interface timing
LRCK/FSYNC
SCLK
(CPOL = 0)
SCLK
(CPOL = 1)
SDIN
tSU:FSYNC
t_{D:CLK–FSYNC}
4.TDM interface timing
(shown with xSP_FSD = 010, xSP_LCHI = 1)
LRCK/FSYNC
SCLK
tSU :FSYNC
...
...
...
...
tSU:SDI
tHI:FSYNC
t H: FSYNC
1/Fs
tH:FSYNC
f_SCLK = N · Fs
...
...
1/fSCLK
...
tLO :SCLK
t_HI:SCLK
...
tH:SDI
1 /Fs
fSCLK = N · Fs
...
1/fSC LK
...
SDIN
tD :C LK- FSYN C
Don’t Care
tL O:SC LK
tH I:SC L K
Frame location 0
Frame location N -1
...
tSU:SDI
t H: SDI
5.Applies to Master and Slave Modes, unless specified otherwise.
6.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK high (xSP_LCHI) is set to
768 SCLK periods and LRCK period (xSP_LCPR) is set to 769 SCLK periods.
7.Data may be latched/launched on either the rising or falling edge of SCLK.
8.SCLK duty cycle in Master Mode depends on Master Mode clock configuration, and can vary by up to 1 MCLK_EXT period.
9.Data is latched/launched on the rising or falling edge of SCLK as determined by xSP_SCPOL_OUT, xSP_SCPOL_IN, and xSP_FSD bits. See the
SCLK launching specs in Table 3-18.
Table 3-19. DSD Switching Characteristic
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43130 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;
parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =
1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; T_A = +25°C; C_L = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at V_OL and V_OH
thresholds (see Table 3-11).
Parameter ^1,2
Symbol
DSDCLK duty cycle
—
DSDCLK pulse width low
DSDCLK pulse width high
DSDCLK frequency
(64× oversampled)
(128× oversampled)
t_SCLKL
t_SCLKH
—
DSDA/DSDB valid to DSDCLK rising setup time
DSDCLK rising to DSDA or DSDB hold time
DSD clock to data transition (Phase Modulation Mode)
t_SDLRS
t_SDH
t_DPM
1.Serial audio input interface timing
Minimum
40
80
80
1.024
2.048
20
20
–20
Typical
—
—
—
2.8224
5.6448
—
—
—
Maximum
60
—
—
f_{MCLK_INT}/8
f_{MCLK_INT}/4
—
—
20
Units
%
ns
ns
MHz
MHz
ns
ns
ns
tSCLKL
tSCLKH
DSDCLK
tSDLRS
tSDH
2.Phase modulation mode serial audio input interface timing
DSDA,
DSDB
DSDCLK
(128•Fs)
tDPM
tDPM
DSDCLK
(64•Fs )
DSDA,
DSDB
22
DS1073F1