CS43130 Datasheet, PDF (23/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
3 Characteristics and Specifications
Table 3-20. I²C Slave Port Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to
ground; VL = 1.8 V; inputs: Logic 0 = GNDA = 0 V, Logic 1 = VL; T_A = +25°C; SDA load capacitance equal to maximum value of C_B = 400 pF; minimum
SDA pull-up resistance, R_P(min).¹ Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS43130
with the specified load capacitance.
Parameter ²
Symbol ³
Minimum Maximum Units
SCL clock frequency
Clock low time
Clock high time
Start condition hold time (before first clock pulse)
Setup time for repeated start
Rise time of SCL and SDA
Standard Mode
Fast Mode
Fast Mode Plus
f_SCL
t_LOW
t_HIGH
t_HDST
t_SUST
t_RC
—
1000
kHz
500
—
ns
260
—
ns
260
—
ns
260
—
ns
—
1000
ns
—
300
ns
—
120
ns
Fall time of SCL and SDA
Standard Mode
t_FC
Fast Mode
Fast Mode Plus
—
300
ns
—
300
ns
—
120
ns
Setup time for stop condition
SDA setup time to SCL rising
SDA input hold time from SCL falling ⁴
Output data valid (Data/Ack) ⁵
Standard Mode
Fast Mode
Fast Mode Plus
t_SUSP
t_SUD
t_HDDI
t_VDDO
260
—
ns
50
—
ns
0
—
ns
—
3450
ns
—
900
ns
—
450
ns
Bus free time between transmissions
SDA bus capacitance
t_BUF
SCL frequency = 1 MHz, V_L = 1.8 V
C_B
SCL frequency ≤ 400 kHz
500
—
ns
—
400
pF
—
400
pF
SCL/SDA pull-up resistance ¹
Pulse width of spikes to be suppressed
Switching time between RCO and MCLK_INT ⁶
V_L = 1.8 V
R_P
t_PS
—
350
—
Ω
—
50
ns
150
—
µs
Power-up delay (delay before I²C can communicate after RESET released)
t_PUD
1500
—
µs
1.The minimum R_P value (resistor shown in Fig. 2-1) is determined by using the maximum level of VL, the minimum sink current strength of its
respective output, and the maximum low-level output voltage V_OL. The maximum R_P value may be determined by how fast its associated signal must
transition (e.g., the lower the value of R_P, the faster the I²C bus is able to operate for a given bus load capacitance). See I²C bus specification
referenced in Section 13.
2.All timing is relative to thresholds specified in Table 3-11, V_IL and V_IH for input signals, and V_OL and V_OH for output signals.
3.I²C control-port timing
Repeated
Stop Start
Start
Stop
SDA
SCL
t_BUF
t_HDST
t_HIGH
t_HDST
t_FC
t_SUSP
tLOW
t_VDDO
t_SUD
tSUST
t_RC
t_HDDI
4.Data must be held long enough to bridge the transition time, t_F, of SCL.
5.Time from falling edge of SCL until data output is valid.
6.Upon setting MCLK_SRC_SEL and sending the I²C stop condition, the switching of RCO and other MCLK_INT sources occurs. A least wait
time as specified is required after changing MCLK_SRC_SEL and sending the I²C stop condition before the next I²C transaction is initiated.
DS1073F1
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