CS43130 Datasheet, PDF (36/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.6 Clocking Architecture
4.5.2.1 AC Load Detection
The CS43130 can also measure the headphone load impedance in the frequency range of 20 Hz to 20 kHz. The required
conditions before the measurement is similar to the low frequency load measurement, with one exception—HPLOAD_
MEAS_FREQ is set at the frequency of interest. Refer to Section 7.5.11 and Section 7.5.12 for details.
After HPLOAD_AC_START bit is cleared and set:
1. HPLOAD_AC_BUSY bit is set
2. The result of the measured resistance is reported in RL_AC_STAT.
3. HPLOAD_AC_DONE_INT is set and the interrupt is triggered.
For each headphone, the low-frequency load measurement must be performed (as indicated by the HPLOAD_DC_ONCE
bit) before any impedance is measured at other frequencies. If the low-frequency load measurement is not performed and
the process is initiated by pulsing the HPLOAD_AC_START bit low and high, the CS43130 can not generate a test signal
and sets the HPLOAD_NO_DC_INT error interrupt bit. Any RL_AC_STAT value should be treated as invalid.
Once the HPLOAD_MEAS_FREQ is set to a non-zero value and HPLOAD_EN = 1, a tone at the specified frequency is
applied on the headphone load. Because the test tone is in the audio frequency range, it can be audible by the headphone
user. It is recommended that the user system notify the headphone user of the expected events before initiating this
measurement.
For each frequency, the measurement completion time is affected by the frequency of interest. The lower the frequency,
the longer the measurement time. For the relationship between the frequency under test and the measurement time, the
following applies:
• For frequencies under test less than 6 kHz or when the CS43130 comes out of reset, measurement time is up to
11 periods of the test tone.
• For frequencies under test between 6 and 13 kHz, measurement time is up to 22 periods of the test tone.
• For frequencies under test between 13 and 20 kHz, measurement time is up to 33 periods of the test tone.
See Section 5.11.3 for example code of AC impedance measurement.
4.6 Clocking Architecture
4.6.1 Master Clock (MCLK) Sources
The MCLK is required by the CS43130 to operate any functionality associated with control, serial-port operation, or data
conversion. Depending on the setting of MCLK_SRC_SEL (see p. 96), the MCLK can be provided by one of following
methods:
• Sourced from a crystal oscillator between XTI/MCLK and XTO pins (see Fig. 4-12), then used directly as MCLK_INT
• Externally sourced through the XTI/MCLK input pin (see Fig. 4-13)
• PLL reference clock is provided through the XTI/MCLK input pin (see Fig. 4-13), then use internal PLL to convert
into MCLK_INT
• Use internal RCO as MCLK. Note that for optimized power consumption, the HPIN input path is the only supported
audio playback feature in this mode. Also, this mode can support HP detection and I²C communication. DAC
playback and headphone impedance measurement functions are not supported.
XTAL
XTI/MCLK
XTO
Figure 4-12. System Clocking—Crystal Mode
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