CS43130 Datasheet, PDF (66/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
Example 5-11. Startup to I²S Playback (Cont.)
STEP
TASK
28 Configure Headphone
detect
REGISTER/BIT FIELDS
HP Detect. 0xD0000
HPDETECT_CTRL
HPDETECT_INV
HPDETECT_RISE_DBC_TIME
HPDETECT_FALL_DBC_TIME
Reserved
VALUE
0x04
00
0
00
10
0
DESCRIPTION
HP detect disabled
HP detect input is not inverted
Tip sense rising debounce time set to 0 ms
Tip sense falling debounce time set to 500 ms
29 Headphone detect
HP Detect. 0xD0000
0xC4
HPDETECT_CTRL
HPDETECT_INV
HPDETECT_RISE_DBC_TIME
HPDETECT_FALL_DBC_TIME
Reserved
11 HP detect enabled
0 HP detect input is not inverted
0 0 Tip sense rising debounce time set to 0 ms
10 Tip sense falling debounce time set to 500 ms
0
30 Enable interrupts
31 Read Interrupt Status 1 register (0xF0000) and Interrupt Status 2 register (0xF0001) to clear sticky bits.
32 Enable headphone detect Interrupt Mask 1. 0xF0010
interrupts
DAC_OVFL_INT_MASK
HPDETECT_PLUG_INT_MASK
HPDETECT_UNPLUG_INT_MASK
XTAL_READY_INT_MASK
XTAL_ERROR_INT_MASK
PLL_READY_INT_MASK
PLL_ERROR_INT_MASK
PDN_DONE_INT_MASK
0x87
1
0
0
0
0
1
1
1
Enable HPDETECT_PLUG interrupt
Enable HPDETECT_UNPLUG interrupt
33 Enable ASP interrupts Interrupt Mask 2. 0xF0011
0x07
ASP_OVFL_INT_MASK
ASP_ERROR_INT_MASK
ASP_LATE_INT_MASK
ASP_EARLY_INT_MASK
ASP_NOLRCK_INT_MASK
Reserved
0 Enable ASP_OVFL interrupt
0 Enable ASP_ERROR interrupt
0 Enable ASP_LATE interrupt
0 Enable ASP_EARLY interrupt
0 Enable ASP_NOLRCK interrupt
111
34 Wait for interrupt. Check if XTAL_READY_INT = 1 in Interrupt Status 1 register (0xF0000).
35 Switch MCLK source to
XTAL
System Clocking Control 1. 0x10006
Reserved
MCLK_INT
MCLK_SRC_SEL
0x04
0000 0 MCLK Source set to XTAL. MCLK_INT frequency set to
1 22.5792 MHz
00
36 Wait at least 150 µs.
37 Enable ASP clocks
Pad Interface Configuration. 0x1000D
0x02
Reserved
XSP_3ST
ASP_3ST
0000 00
1 XSP Interface status is don't care (set to default)
0 Enable serial clocks in Master Mode
38 Power up HP
Refer to Ex. 5-9 for PCM power-up sequence. Skip Step 1 of Ex. 5-9 (completed in Step 8 above).
5.10.2 Power-Up Sequence to DSD Playback
In Ex. 5-12, a 22.5792-MHz crystal is used, the PLL is used to create a 24.576-MHz MCLK, XSP is set as DSD slave at
2.8224 MHz, and full-scale output is 1.732 Vrms.
Example 5-12. Startup to DSD Playback
STEP
TASK
REGISTER/BIT FIELDS
1 _{Apply all relevant power supplies, then assert RESET.}
2 Wait for 1.5 ms
3 Configure XTAL driver
4 Configure XTAL bias current Crystal Setting. 0x20052
strength (assuming River Crystal
at 22.5792 MHz)
Reserved
XTAL_IBIAS
5 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts.
6 Enable XTAL interrupts
Interrupt Mask 1. 0xF0010
DAC_OVFL_INT_MASK
HPDETECT_PLUG_INT_MASK
HPDETECT_UNPLUG_INT_MASK
XTAL_READY_INT_MASK
XTAL_ERROR_INT_MASK
PLL_READY_INT_MASK
PLL_ERROR_INT_MASK
PDN_DONE_INT_MASK
VALUE
0x04
0000 0
100
0xE7
1
1
1
0
0
1
1
1
DESCRIPTION
Bias current set to 12.5 µA
Enable XTAL_READY interrupt
Enable XTAL_ERROR interrupt
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DS1073F1