CS43130 Datasheet, PDF (21/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
3 Characteristics and Specifications
Table 3-16. DC Characteristics (Cont.)
Test conditions (unless otherwise specified): Fig. 2-1 shows CS43130 connections; GNDD = GNDA = GNDCP = 0 V; all voltages with respect to ground.
Other DC filter characteristics
Parameters
FILT+ voltage
FILT– voltage
HP output current limiter on threshold.
VD power-on
reset threshold
(V_POR)
Minimum
—
—
—
Up
—
Down
—
Typical
–0.35
0.35
120
1.15
0.950
Maximum
—
—
160
—
—
Units
V
V
mA
V
V
Table 3-17. Power Consumption
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43130 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;
performance data taken with VA = VCP = VD = VL = 1.8 V; VP = 3.6 V; T_A = +25°C; ASP_SPRATE = 0001(44.1-kHz mode); MCLK_INT= 1
(22.5792 MHz); MCLK_SRC_SEL = 00; all other fields are set to defaults; no signal on any input; control port inactive; all serial ports are set to Slave or
Master Mode as indicated, input clock/data are held low unless active; test load is R_L = 32  and C_L = 1 nF for HPOUTx; measured values include currents
consumed by the DAC and do not include current delivered to external loads unless specified otherwise (e.g., from HPOUTx outputs); see Fig. 2-1.
Use Cases
P_OUT
Typical Current (µA)
Total
i_VCP
i_VA
i_VD
i_VL
i_VP
Power
(µW)
1 Off ¹
—
0
0
0
0
6
22
2 Standby ²
HPDETECT enabled
—
0
0
256
0
32
576
3 A Playback
B
External MCLK = 22.5792 MHz, I²S/DoP Quiescent ³
4021 7302 1444 40
32
23167
Stereo HPOUT
0.1mW
12363 7862 2004 40
32
40199
4 Alternate HP path stereo HPIN enabled ⁴
Quiescent
209
110
393
3
66
1524
1.Off configuration: Clock/data lines held low; RESET = LOW; VA = VD = VL = 0 V, VCP = 0 V, VP = 3.6 V.
2.Standby configuration: Clock/data lines held low; RESET = HIGH; VA = VD = VL = 1.8 V, VCP = 1.8 V, VP = 3.6 V; HP_DETECT_CTRL = 11 (enabled);
HPDETECT_PLUG_INT_MASK=0 (unmasked); PDN_XTAL = 1, MCLK_SRC_SEL = 10 (RCO selected as MCLK source).
3.Quiescent configuration: data lines held low; RESET = HIGH; VA = 1.8 V, VD = VL = VCP = 1.8 V, VP = 3.6 V. Serial port, I²S/DoP Mode (ASP and
SDIN, ASP_M/Sb = 0); PDN_XTAL = 1.
4.Quiescent configuration: PDN_XTAL = 1; MCLK_SRC_SEL = 10 (RCO selected as MCLK source); alternate headphone path (PDN_HP = 1, HPOUT_
CLAMP = 1, HP_IN_EN = 1); data lines held low; RESET = HIGH; VA = 1.8 V, VD = VL = VCP = 1.8 V, VP = 3.6 V.
Table 3-18. Serial-Port Interface Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43130 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;
parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =
1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; T_A = +25°C; C_L = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at V_OL and V_OH thresholds
(see Table 3-11).
Parameters ^1,2,3,4,5
Symbol
FSYNC frame rate
Fs
FSYNC high period ⁶
t_HI:FSYNC
Master
Mode
FSYNC duty cycle
xSP_5050 = 1
—
FSYNC delay time after SCLK launching edge ⁷
t_{D:CLK–FSYNC}
SCLK frequency
f_SCLK
SCLK high period ⁸
t_HI:SCLK
Slave
Mode
SDIN setup time before SCLK latching edge ⁷
SDIN hold time after SCLK latching edge ⁷
FSYNC setup time before SCLK latching edge ⁷
FSYNC hold time after SCLK latching edge ⁷
SCLK frequency
SCLK high period
SCLK low period
SDIN setup time before SCLK latching edge ⁹
SDIN hold time after SCLK latching edge ⁷
t_SU:SDI
t_H:SDI
t_SU:FSYNC
t_H:FSYNC
f_SCLK
t_HI:SCLK
t_LO:SCLK
t_SU:SDI
t_H:SDI
Minimum
Typical
Maximum
(See Section 4.9.5)
1/f_SCLK
45
—
(n–1)/f_SCLK
—
55
—
—
20
—
—
f_{MCLK_INT}
11//(f2_M•_Cf_{SLCKL_KIN}) _T–
—
11/(/f2_M•_Cf_{SLCKL_KIN}) _T+
10
—
—
5
—
—
10
—
—
5
—
—
—
—
24.58
16
—
—
16
—
—
10
—
—
5
—
—
Units
kHz
s
%
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
1.MCLK in this table refers to the external clock supplied to the MCLK pin (MCLK_EXT).
2.Output clock frequencies follow the master clock (MCLK_EXT) frequency proportionally. Any deviation of the clock source from the nominal supported
rates are directly imparted to the output clock rate by the same factor (e.g., +100-ppm offset in the frequency of MCLK_EXT becomes a +100-ppm
offset in LRCK/FSYNC and SCLK).
DS1073F1
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