CS43130 Datasheet, PDF (60/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

Example 5-5. PCM Power Down Sequence (Cont.)
STEP
TASK
8 Power down ASP
REGISTER/BIT FIELDS
Power Down Control. 0x20000
9 Unmute
PDN_XSP
PDN_ASP
PDN_DSDIF
PDN_HP
PDN_XTAL
PDN_PLL
PDN_CLKOUT
Reserved
PCM Path Signal Control 1. 0x90003
10 Restore defaults
PCM_RAMP_DOWN
PCM_VOL_BEQA
PCM_SZC
Reserved
PCM_AMUTE
PCM_AMUTEBEQA
PCM_MUTE_A
PCM_MUTE_B
0xC0002
0xC000E
0xC0009
0x10010
CS43130
5.7 Headphone Power Down Sequences
VALUE
data(0x20000)
OR (0x40)
DESCRIPTION
x
1
Turn off ASP
x
x
x
x
x
x
data(0x90003)
AND (0xFC)
x
x
x
x
x
x
0
Unmute channel A
0
Unmute channel B
0x10
0x00
0x16
0x00
5.7.2 DSD Power Down Sequence
Example 5-6. DSD Power Down Sequence
STEP
TASK
1 Enable PDN_DONE
interrupt
REGISTER/BIT FIELDS
Interrupt Mask 1. 0xF0010
VALUE
data(0xF0010)
AND (0xFE)
DESCRIPTION
DAC_OVFL_INT_MASK
HPDETECT_PLUG_INT_MASK
HPDETECT_UNPLUG_INT_MASK
XTAL_READY_INT_MASK
XTAL_ERROR_INT_MASK
PLL_READY_INT_MASK
PLL_ERROR_INT_MASK
PDN_DONE_INT_MASK
x
x
x
x
x
x
x
0
Enable PDN_DONE interrupt
2 Pop-free power down 0x10010
0x99
0xC0002
0x12
0xC000E
0x02
0xC0009
0x12
3 Mute
DSD Processor Path Signal Control 1. 0x70002 data(0x70002)
OR (0x03)
Reserved
DSD_VOL_BEQA
DSD_SZC
Reserved
DSD_AMUTE
DSD_AMUTEBEQA
DSD_MUTE_A
DSD_MUTE_B
x
x
x
x
x
x
1
Mute channel A
1
Mute channel B
4 Wait time delay. If DSD_SZC = 1, then delay = (255 - max(DSD_VOLUME_A, DSD_VOLUME_B)) / 2 ms. Else, delay = 130 ms.
5 Power down amplifier Power Down Control. 0x20000
data(0x20000)
OR (0x10)
PDN_XSP
PDN_ASP
PDN_DSDIF
PDN_HP
PDN_XTAL
PDN_PLL
PDN_CLKOUT
Reserved
x
x
x
1
Turn off HP
x
x
x
x
6 Wait for interrupt. Check for PDN_DONE_INT = 1 in Interrupt Status 1 register (0xF0000).
7 Reset data buffer
0x90097
0x01
60
DS1073F1