CS43130 Datasheet, PDF (25/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.1 Overview
4.1.5 Audio Interfaces and Supported Formats
There are two serial input ports on the CS43130, the audio serial port (ASP) and the auxiliary serial port (XSP). The ASP
on the CS43130 supports I²S, TDM, and DoP (DSD over PCM) formats up to a 384-kHz sample rate. The XSP on the
CS43130 supports the DoP format up to a 352.8-kHz sample rate.
The CS43130 also has a dedicated DSD interface to support up to 128•Fs. The DSD interface shares pins with the XSP.
4.1.6 System Clocking
The CS43130 internal MCLK can be sourced from three options:
• Direct MCLK/crystal mode. The internal MCLK is provided through XTI/MCLK pin directly or generated by crystal
oscillator.
• PLL mode. A PLL reference CLK is provided externally through XTI/MCLK. The PLL is configured, and output is
used as the internal MCLK.
• RCO mode. An internal RCO is used as the internal MCLK. Note that HPIN input path is the only supported audio
playback feature in this mode for optimized power consumption. This mode can also support HP detection and I²C
communication. DAC playback and headphone impedance measurement function s are not supported.
The clock output is provided for audio applications that require high quality audio rate system clock. This clock output can
be sourced from the following two options:
• The clock generated by the CS43130 crystal oscillator.
• Output of the internal Fractional-N PLL that refers to MCLK input. See Section 4.7.1 for supported frequencies.
The internal MCLK is used to generate serial port clocks. See Table 4-6 for supported LRCK combinations.
4.1.7 System Interrupts
The CS43130 includes an open-drain interrupt output (INT pin). Interrupt mask registers control whether an event
associated with an interrupt status/mask bit pair triggers the assertion of INT. All types of interrupts are described in
Section 4.11.
4.1.8 System Reset
The CS43130 offers two types of reset options:
• Asserting RESET. If RESET is asserted, all registers and all state machines are immediately set to their default
values/states. No operation can begin until RESET is deasserted. Before normal operation can begin, RESET must
be asserted at least once after the VP supply is first brought up.
• Power-on reset (POR). If the VD supply is lower than the POR threshold specified in Table 3-16, the VD register
fields and the state machines are held in reset, setting them to their default values/states. The POR releases the
reset when the VD supply goes above the POR threshold. When the VD supply is turned on, the VL and VA supplies
must also be turned on at the same time.
4.1.9 Power Down
The CS43130 has a register byte to power down individual components on the chip. Before any change can be applied to
an individual component (except PLL), the block must be powered down first. For the PLL, changes can be applied after
PLL_START is cleared.
The PDN_HP bit is responsible for enabling or disabling the playback signal chain operation. All the necessary
components for playback operation need to be powered up and configured properly before PDN_HP is cleared. To disable
the playback signal chain, PDN_HP is set. PDN_HP needs to be set before making any changes to the playback signal
chain setup, except the following functions:
• Volume and mute related functions
• PCM filter settings (see Section 7.5.2)
DS1073F1
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