CS43130 Datasheet, PDF (70/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
Example 5-13. DoP Playback with PLL (Cont.)
STEP
TASK
19 Set ASP numerator
REGISTER/BIT FIELDS
ASP Numerator 1. 0x40010
ASP_N_LSB
VALUE
0x03
0x03
ASP Numerator 2. 0x40011
ASP_N_MSB
0x00
0x00
20 Set ASP denominator
ASP Denominator 1. 0x40012
ASP_M_LSB
0x08
0x08
ASP Denominator 2. 0x40013
ASP_M_MSB
0x00
0x00
21 Set ASP LRCK high time
ASP LRCK High Time 1. 0x40014
0x17
ASP_LCHI_LSB
0x17
ASP LRCK High Time 2. 0x40015
0x00
ASP_LCHI_MSB
0x00
22 Set ASP LRCK period
ASP LRCK Period 1. 0x40016
0x2F
ASP_LCPR_LSB
0x2F
ASP LRCK Period 2. 0x40017
0x00
ASP_LCPR_MSB
0x00
23 Configure ASP clock
ASP Clock Configuration. 0x40018 0x1C
Reserved
000
ASP_M/SB
1
ASP_SCPOL_OUT
1
ASP_SCPOL_IN
1
ASP_LCPOL_OUT
0
ASP_LCPOL_IN
0
24 Configure ASP frame
ASP Frame Configuration. 0x40019 0x0A
Reserved
000
ASP_STP
0
ASP_5050
1
ASP_FSD
010
25 Set ASP channel location
ASP Channel 1 Location. 0x50000 0x00
ASP_RX_CH1
0x00
ASP Channel 2 Location. 0x50001 0x00
ASP_RX_CH2
0x00
26 Set ASP channel size and enable
ASP Channel 1 Size and Enable.
0x5000A
0x06
Reserved
ASP_RX_CH1_AP
ASP_RX_CH1_EN
ASP_RX_CH1_RES
0000
0
1
10
ASP Channel 2 Size and Enable.
0x5000B
0x0E
Reserved
ASP_RX_CH2_AP
ASP_RX_CH2_EN
ASP_RX_CH2_RES
0000
1
1
10
27 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000).
28 Configure DSD processor
29 Configure DSD volume
DSD Volume A. 0x70001
0x00
DSD_VOLUME_A
0x00
30 Configure DSD Path Signal Control 1
DSD Processor Path Signal Control 1. 0xEC
0x70002
Reserved
1
DSD_VOL_BEQA
1
DSD_SZC
1
Reserved
0
DSD_AMUTE
1
DSD_AMUTE_BEQA
1
DSD_MUTE_A
0
DSD_MUTE_B
0
DESCRIPTION
LSB of ASP sample rate fractional divide
numerator
MSB of ASP sample rate fractional divide
numerator
LSB of ASP sample rate fractional divide
denominator
MSB of ASP sample rate fractional divide
denominator
LSB of ASP LRCK high time duration
MSB of ASP LRCK high time duration
LSB of ASP LRCK period
MSB of ASP LRCK period
Set ASP port to be Master
Set output SCLK polarity
Input SCLK polarity is don't care
Set Output LRCK polarity
Input LRCK polarity is don't care
Configure ASP port to accept I²S input
ASP Channel 1 starts on SCLK0
ASP Channel 2 starts on SCLK0
ASP Channel 1 active phase
ASP Channel 1 enable
ASP Channel 1 size is 24 bits
ASP Channel 2 active phase
ASP Channel 2 enable
ASP Channel 2 size is 24 bits
Channel A volume set to 0 dB
DSD Volume B equals DSD volume A
Soft ramp control enabled
Mute occurs after 256 repeated 8-bit DSD mute
patterns
Mute happens only when mute pattern is detected
in both channels
Function is disabled
Function is disabled
70
DS1073F1