CS43130 Datasheet, PDF (46/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.9 Audio Serial Port (ASP)
Fig. 4-24 shows how LRCK frame start delay (xSP_FSD) controls the number of SCLK periods delay from the LRCK
synchronization edge to the start of frame data.
FSD = 101
FSD = 100
LRCK
FSD = 011
FSD = 010
FSD = 001
FSD = 000
SCPOL _IN = 0
SCPOL_OUT = 0
SCPOL _IN = 1
SCPOL_OUT = 0
SCLK
SDIN
SCLK
SDIN
...
...
...
...
...
...
0
0.5
1
1.5
2
2.5
...
0 1 2 3 4 5 6 7 8 9 ^...N-5 N-4 N-3 N-2 N-1
Channel location (xSP_RX_CHn) = 0
End of frame
...
0 1 2 3 4 5 6 7 8 9 ^...N-5 N-4 N-3 N-2 N-1
Channel location (xSP_RX_CHn) = 0
End of frame
SCPOL _IN = 0
SCPOL_OUT = 1
SCLK
SDIN
...
0 1 2 3 4 5 6 7 8 9 ^...N-5 N-4 N-3 N-2 N-1
Channel location (xSP_RX_CHn) = 0
End of frame
SCPOL _IN = 1
SCPOL_OUT = 1
SCLK
...
SDIN
0 1 2 3 4 5 6 7 8 9 ^...N-5 N-4 N-3 N-2 N-1
Channel location (xSP_RX_CHn) = 0
End of frame
Figure 4-24. LRCK FSD and SCLK Polarity Example Diagram
Table 4-6. Serial Port Clock Generation—Supported Configurations for 32 bits and 2 Channels
Frequency (MHz)
22.5792
24.576
LRCK/FSYNC
Rate (kHz)
SCLKs per LRCK Frame
xSP_LCPR + 1 xSP_LCPR[10:0]
xSP_N[15:0]
xSP_M[15:0]
32.000
64
63
40
441
44.100
64
63
1
8
48.000
64
63
20
147
88.200
64
63
1
4
96.000
64
63
40
147
176.400
64
63
1
2
192.000
64
63
80
147
352.800
64
63
1
1
32.000
64
63
1
12
44.100
64
63
147
1280
48.000
64
63
1
8
88.200
64
63
147
640
96.000
64
63
1
4
176.400
64
63
147
320
192.000
64
63
1
2
352.800
64
63
147
160
384.000
64
63
1
1
46
DS1073F1