CS43130 Datasheet, PDF (56/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5 Applications
5 Applications
This section provides recommended application procedures and instruction sequences for standard CS43130 operations.
5.1 PLL Clocking
Data-path logic is in the MCLK_INT domain, where MCLK_INT is expected to be 22.5792 or 24.576 MHz. For clocking
scenarios in which the external system MCLK provided to CS43130 is neither 22.5792 nor 24.576 MHz, the PLL must be
turned on to provide the desired internal MCLK. At start up, the system uses RCO as the internal MCLK for PLL
programming over I²C and switches to the PLL output after it settles. PLL start-up time is a maximum of 1 ms.
5.2 Power Sequencing
Note the following for power-up sequencing on the CS43130:
• VP must be powered up first.
• All other supplies can come up in any order before RESET is released.
Note the following for power-down sequencing on the CS43130:
• After RESET is asserted, VA/VCP/VL/VD can be removed in any order.
• VP must be powered down last.
5.3 Crystal Tuning
The CS43130 uses an external crystal as the source for internal MCLK. Refer to Table 3-14 for the load capacitance that
is supported by CS43130. Table 5-1 lists supported crystals that meet the requirements for CS43130 and also shows also
shows the XTAL_IBIAS settings for different crystals.
Table 5-1. Example List of Supported Crystals
Manufacturer ¹
River Electronics
NDK
TXC
Part Number ¹
FCX-06-22.5792J51933
FCX-06-24.5760J51930
NX2016SA 22.5792M EXS00A-CS09116
NX2016SA 24.576M EXS00A-CS09117
8Y22570001
8Y24570001
Frequency (MHz)
22.5792
24.576
22.5792
24.576
22.5792
24.576
Bias Current
Strength (µA)
12.5
7.5
15
12.5
1.Contact your local Cirrus Logic representative for a list of supported manufacturers and part numbers.
Crystal Setting Register
(0x20052)
0x04
0x06
0x02
0x04
The crystal setting register (0x20052) must be set appropriately based on the crystal used.
The frequency at which the crystal eventually oscillates can be calculated using the formula below:
where
F_osc= 1/(2*π*sqrt[Lm*(C_m (C₀+C_L))/(C_m+C₀+C_L)]) ,
L_m = motional inductance of crystal
C_m = motional capacitance of crystal
C₀ = shunt capacitance
C_L = load capacitance
Trace capacitance and pad capacitance (approximately 0.5 pF) must also be taken into account while calculating the value
of the load capacitors. Below are the steps to tune the crystal to the correct frequency:
1. Select load capacitor values that match the load capacitance spec in crystal manufacturer's data sheet.
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