CS43130 Datasheet, PDF (6/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

1.3 Pin Descriptions
CS43130
1.3 Pin Descriptions
Table 1-1. Pin Descriptions
Pin Name
QFN
Pin #
WLCSP
Ball
Power
Supply
I/O
Pin Description
Internal Digital I/O Digital I/O
Connection Driver Receiver
ADR
30
CLKOUT 33
SCLK1
34
LRCK1
38
SDIN1
2
DSDA/
40
SDIN2
DSDB/
29
LRCK2
DSDCLK/ 32
SCLK2
INT
27
RESET
28
SDA
39
SCL
1
XTI/MCLK 37
XTO
36
FILT+
5
FILT–
6
HP_
22
DETECT
HPINB
15
HPINA
12
HPOUTB 16
HPOUTA 14
Digital I/O
C2
VL I Address Bit (I²C). In I²C Mode, ADR is a chip address pin.
—
—
—
B2
VL O CLK Output. Single-ended clock output sourced from PLL or
Weak
CMOS
—
buffered crystal.
pull-down output
A2
VL I/O Serial Audio Input Bit Clock 1. Serial bit clock for audio data on Weak
CMOS Hysteresis
the SDIN pins.
pull-down output on CMOS
input
B3
VL I/O Serial Audio Input Left/Right Clock. Word-rate clock for the
Weak
CMOS Hysteresis
audio data on the SDIN pins.
pull-down output on CMOS
input
A6
VL I Serial Audio Input Data Port. Audio data serial input pin 1.
Weak
pull-down
— Hysteresis
on CMOS
input
A5
VL I DSD Data Input A/Serial Data In 2. DSD audio or PCM audio
Weak
data serial input pin 2.
pull-down
— Hysteresis
on CMOS
input
C1
VL I/O DSD Data Input B/Serial Audio Input Left/Right Clock 2. DSD Weak
CMOS Hysteresis
audio data serial input pin or word rate clock for the audio data on pull-down output on CMOS
the SDIN2 pin.
input
B1
VL I/O DSD Clock Input/Serial Audio Input Bit Clock 2. DSD clock
Weak
CMOS Hysteresis
input. Serial bit clock for audio data on the SDIN2 pin.
pull-down output on CMOS
input
C5
VP O Interrupt. When pulled up, works as system interrupt pin. Open
drain, active low programmable.
—
CMOS
—
open-drain
output
C4
VP I System Reset. The device enters system reset when enabled.
—
— Hysteresis
on CMOS
input
B4
VL I/O Serial Control Data I/O (I²C). In I²C Mode, SDA is the control I/O
—
CMOS Hysteresis
data line.
open-drain on CMOS
output
input
B5
VL I Software Clock (I²C). Serial control interface clock used to clock
—
control data bits into and out of the CS43130.
— Hysteresis
on CMOS
input
A4
VL I Crystal/Oscillator Input/MCLK In. Crystal or digital clock input
Weak
for the master clock.
pull-down
— Hysteresis
on CMOS
input
A3
VL O Crystal/Oscillator Output. Crystal output.
Weak
CMOS
—
pull-down output
Analog I/O
D4
VA O Positive/Negative Voltage Reference. Positive/negative
D5
reference voltage for DAC.
—
—
—
F4
VP I Headphone Detect. Can be configured to be debounced on
unplugged and plugged events before it is presented as a
noninterrupt status bit (HPDETECT).
—
Hi-Z
—
F3 VCP_ I Headphone Audio Input. For interfacing low power audio source, Weak
—
—
G5 ^FILT±
an alternate analog input path for the headphone output. Refer to pull-down
analog specification table for full-scale input level.
G3 VCP_ O Headphone Audio Output. Refer to analog specification table for
—
G4 ^FILT±
full-scale output level.
—
—
HPREFB 17
HPREFA 13
E3 VCP_ I Headphone Output Reference. Reference for headphone
E4 ^FILT±
amplifier and detect.
—
—
—
Power Supplies
VL
31
A1
N/A I Logic Power. Input/Output power supply, typically +1.8 V.
—
—
—
6
DS1073F1