CS43130 Datasheet, PDF (13/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
3 Characteristics and Specifications
Table 3-4. Analog Output Characteristics (HV_EN = 1) ¹ (Cont.)
Test conditions (unless otherwise specified): Fig. 2-1 shows CS43130 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless
specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; HV_EN = 1; ASP_M/Sb = 1; typical, min/max performance
data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK
= 44.1-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency f_XTAL = 22.5792 MHz); Volume = 0 dB; when testing
in DSD processor mode, DSD_ZERODB = 1; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external
impedance on HPREFx.
PCM and DSD Processor Mode Parameter ^2,3,4
Other characteristics Interchannel gain mismatch (defined in Table 3-1)
for HPOUTx
Interchannel phase mismatch (defined in Table 3-1)
Output offset voltage: Mute (defined in Table 3-1)
Gain drift (defined in Table 3-1)
Load resistance (R_L)
Load capacitance (C_L)
Turn-on time (defined in Table 3-1)
Click/pop during PDN_HP enable or disable
Minimum
—
—
—
—
600
—
—
A-weighted —
Typical
±0.1
±0.05
±0.5
±100
—
—
—
—
Maximum Units
—
dB
—
°
±1
mV
—
ppm/°C
—

1
nF
10
ms
–60
dBV
1.This table also applies to external VCP_FILT supply mode: CS43130 power up procedure is per description in Section 5.10.1; EXT_VCPFILT = 1;
VCP_FILT+ and VCP_FILT– comply to Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN setting becomes don’t care.
2.One LSB of triangular PDF dither is added to PCM data.
3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table.
4.DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index.
5.The volume must be configured as indicated to achieve specified output characteristics.
6.Output test configuration. Symbolized component values are specified in the test conditions.
HPOUTA
HPREFA
Test Load
C_LA
R_LA
+
CH2
–
Measurement
Device
HPREFB
HPOUTB
CLB RLB
–
CH1
+
Table 3-5. Analog Output Characteristics (HV_EN = 0) ¹
Test conditions (unless otherwise specified): Fig. 2-1 shows CS43130 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless
specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; HV_EN = 0; ASP_M/Sb = 1; typical, min/max performance
data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK
= 44.1-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency f_XTAL = 22.5792 MHz); Volume = 0 dB; when testing
in DSD processor mode, DSD_ZERODB = 1; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external
impedance on HPREFx.
HPOUTx;
CR^LL
=
=
10 k
200 pF
OUT_FS = 10
Volume = 0 dB,⁵
unless otherwise
specified
PCM and DSD Processor Mode Parameter ^2,3,4
Dynamic range
(defined in Table 3-1)
24-bit, 32-bit, DSD
16-bit
THD+N
(defined in Table 3-1)
24-bit, 32-bit, DSD
16-bit
Idle channel noise
(A-weighted)
(defined in Table 3-1)
24-bit, 32-bit, DSD
Full-scale output voltage
Interchannel isolation ⁶ (defined in Table 3-1)
Minimum
A-weighted 122
Unweighted 119
A-weighted 91
Unweighted 88
0 dB —
–20 dB —
–60 dB —
0 dB —
–20 dB —
–60 dB —
—
Typical
128
125
97
94
–109
–95
–65
–94
–74
–34
0.55
Maximum
—
—
—
—
–103
—
–59
–88
—
–28
—
Units
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
µV
3.76
217 Hz —
1 kHz —
20 kHz —
3.96
110
94
68
4.16
Vpp
—
dB
—
dB
—
dB
DS1073F1
13