CS43130 Datasheet, PDF (96/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
7.1 Global Registers
7.1.6 System Clocking Control
R/W
7
6
5
4
3
—
Default
0
0
0
0
0
Bits
Name
Description
7:3
—
Reserved
2 MCLK_INT The frequency of internal MCLK.
0 Internal MCLK is expected to be 24.576 MHz
1 (Default) Internal MCLK is expected to be 22.5792 MHz
1:0 MCLK_SRC_ Select the source of internal MCLK.
SEL
00 Direct MCLK/XTAL Mode
01 PLL Mode
10 (Default) RCO Mode
11 Reserved
2
MCLK_INT
1
Address 0x10006
1
0
MCLK_SRC_SEL
1
0
7.1.7 Serial Port Sample Rate
Address 0x1000B
R/W
7
6
5
4
3
2
1
0
—
ASP_SPRATE
Default
0
0
0
0
0
0
0
1
Bits
Name
Description
7:4
—
Reserved
3:0 ASP_SPRATE ASP sample rate. This register must be programmed for both Master Mode and Slave Mode operation.
0000 32 kHz
0001 (Default) 44.1 kHz
0010 48 kHz
0011 88.2 kHz
0100 96 kHz
0101 176.4 kHz
0110 192 kHz
0111 352.8 kHz
1000 384 kHz
1001–1111 Reserved
7.1.8 Serial Port Sample Bit Size
R/W
7
6
5
4
—
Default
0
0
0
0
3
2
XSP_SPSIZE
0
1
Address 0x1000C
1
0
ASP_SPSIZE
0
1
Bits
Name
7:4
—
Reserved
3:2 XSP_SPSIZE XSP sample bit size.
00 32 bits
01 (Default) 24 bits
10–11 Reserved
1:0 ASP_SPSIZE ASP sample bit size.
00 32 bits
01 (Default) 24 bits
10 16 bits
11 8 bits
Description
7.1.9 Pad Interface Configuration
Address 0x1000D
R/W
7
6
5
4
3
2
1
0
—
XSP_3ST
ASP_3ST
Default
0
0
0
0
0
0
1
1
Bits
Name
7:2
—
Reserved
Description
96
DS1073F1