CS43130 Datasheet, PDF (68/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
Example 5-12. Startup to DSD Playback (Cont.)
STEP
TASK
23 Configure DSD Interface
REGISTER/BIT FIELDS
DSD Interface Configuration. 0x70003
VALUE
0x00
DESCRIPTION
Reserved
DSD_M/SB
DSD_PM_EN
DSD_PM_SEL
0000 0
0
0
0
DSD is clock slave
Function is disabled
Function is disabled
24 Configure DSD path Signal
Control 2
DSD Processor Path Signal Control 2.
0x70004
0x13
Reserved
DSD_PRC_SRC
DSD_EN
Reserved
DSD_SPEED
STA_DSD_DET
INV_DSD_DET
0
00
Set source of DSD processor to DSDIF
1
Enable DSD playback
0
0
Set DSD clock speed to 64•FS
1
Static DSD detection enabled
1
Invalid DSD detection enabled
25 Configure HP
26 Configure Class H Amplifier Class H Control. 0xB0000
0x1E
Reserved
ADPT_PWR
HV_EN
EXT_VCPFILT
000
111
Output Signal determines voltage level
1
High Voltage Mode Enabled
0
Using Internal VCPFILT source.
27 Set HP output to full scale
HP Output Control 1. 0x80000
0x30
HP_CLAMPA
HP_CLAMPB
OUT_FS
HP_IN_EN
Reserved
0
0
11
Set headphone output to Full Scale (1.732 V rms)
0
000
28 Configure Headphone Detect HP Detect. 0xD0000
0x04
HPDETECT_CTRL
HPDETECT_INV
HPDETECT_RISE_DBC_TIME
HPDETECT_FALL_DBC_TIME
Reserved
00
HP Detect disabled
0
HP detect input is not inverted
00
Tip Sense rising debounce time set to 0ms
10
Tip sense falling debounce time set to 500ms
0
29 Headphone Detect
HP Detect. 0xD0000
0xC4
HPDETECT_CTRL
HPDETECT_INV
HPDETECT_RISE_DBC_TIME
HPDETECT_FALL_DBC_TIME
Reserved
11
HP Detect enabled
0
HP detect input is not inverted
00
Tip Sense rising debounce time set to 0ms
10
Tip sense falling debounce time set to 500ms
0
30 Enable Interrupts
31 Read Interrupt Status 1 register (0xF0000) and Interrupt Status 5 register (0xF0004) to clear sticky bits
32 Enable Headphone Detect
Interrupts
Interrupt Mask 1. 0xF0010
DAC_OVFL_INT_MASK
HPDETECT_PLUG_INT_MASK
HPDETECT_UNPLUG_INT_MASK
XTAL_READY_INT_MASK
XTAL_ERROR_INT_MASK
PLL_READY_INT_MASK
PLL_ERROR_INT_MASK
PDN_DONE_INT_MASK
0x81
1
0
0
0
0
0
0
1
Unmask HPDETECT_PLUG interrupt and
HPDETECT_UNPLUG interrupt
33 Enable DSD Interrupts
Interrupt Mask 5. 0xF0014
0x03
DSD_STUCK_INT_MASK
DSD_INVAL_A_INT_MASK
DSD_INVAL_B_INT_MASK
DSD_SILENCE_A_INT_MASK
DSD_SILENCE_B_INT_MASK
DSD_RATE_ERROR_INT_MASK
DOP_MRK_DET_INT_MASK
DOP_ON_INT_MASK
0
Enable DSD_STUCK interrupt
0
Enable DSD_INVAL_A interrupt
0
Enable DSD_INVAL_B interrupt
0
Enable DSD_SILENCE_A interrupt
0
Enable DSD_SILENCE_B interrupt
0
Enable DSD_RATE_ERROR interrupt
1
Disable DOP_MRK_DET interrupt
1
Disable DOP_ON interrupt
34 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000)
35 Switch MCLK source to PLL System Clocking Control 1. 0x10006
0x01
Reserved
MCLK_INT
MCLK_SRC_SEL
0000 0
0
01
MCLK Source set to PLL. MCLK_INT frequency set
to 24.576 MHz
36 Wait at least 150 µs
37 Power up HP
Refer to Ex. 5-10 for DSD power-up sequence. Skip Step 1 of Ex. 5-10 (completed in Step 8 above).
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DS1073F1