CS43130 Datasheet, PDF (15/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
3 Characteristics and Specifications
Table 3-5. Analog Output Characteristics (HV_EN = 0) ¹ (Cont.)
Test conditions (unless otherwise specified): Fig. 2-1 shows CS43130 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless
specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; HV_EN = 0; ASP_M/Sb = 1; typical, min/max performance
data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK
= 44.1-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency f_XTAL = 22.5792 MHz); Volume = 0 dB; when testing
in DSD processor mode, DSD_ZERODB = 1; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external
impedance on HPREFx.
PCM and DSD Processor Mode Parameter ^2,3,4
Other characteristics Interchannel gain mismatch (defined in Table 3-1)
for HPOUTx
Interchannel phase mismatch (defined in Table 3-1)
Output offset voltage: Mute (defined in Table 3-1)
Gain drift (defined in Table 3-1)
Load resistance (R_L)
Load capacitance (C_L)
Turn-on time (defined in Table 3-1)
Audio latency after RESET released ⁷
Click/pop during PDN_HP enable or disable
Minimum
—
—
—
—
16
—
—
—
A-weighted —
Typical
±0.1
±0.05
±0.5
±100
—
—
—
—
—
Maximum Units
—
dB
—
degree
±1
mV
—
ppm/°C
—

1
nF
8
ms
20
ms
–60
dBV
1.This table also applies to external VCP_FILT supply mode: CS43130 power up procedure as described in Section 4.3.5; EXT_VCPFILT=1; VCP_
FILT+ and VCP_FILT– comply to Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN setting becomes don’t care.
2.One LSB of triangular PDF dither is added to PCM data.
3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table.
4.DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index.
5.The volume must be configured as indicated to achieve specified output characteristics.
6.HP output test configuration. Symbolized component values are specified in the test
conditions.
HPOUTA
Test Load
C_LA
R_LA
+
CH2
HPREFA
–
Measurement
Device
HPREFB
HPOUTB
CLB RLB
–
CH1
+
7.With I²C normal speed mode and 22.5792-MHz XTAL used as MCLK source, this specification is measured from reset released to when the audio
signal appears on the output per power-up sequence listed in Section 5.10.1. PCM_SZC should be set to Immediate (PCM_SZC = 00) to hear audio
at 20 ms after startup.
Table 3-6. Headphone Load Measurement
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43130 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to
ground; typical performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VL = VD = 1.8 V; min/max performance data taken with VP = 3.6 V,
VCP = VA = 1.8 V, VL = VD = 1.8 V; TA = +25°C. MCLK_INT = 1, PDN_XTAL = 0, and MCLK_SRC_SEL = 00 (crystal frequency f_XTAL = 22.5792 MHz)
Parameters
Frequency range
Frequency resolution
Low frequency impedance range
Relative impedance measurement capability ¹
Impedance measurement accuracy ³
Gain error
Offset
Symbol
—
—
—
—
—
—
Minimum
20
—
8
–12 ²
–5
–1
Typical
—
5.94
—
—
—
—
Maximum Units
20k
Hz
—
Hz
1200

+12
dB
+5
%
1

1.Impedance measurement range is relative to low-frequency HP load impedance measured.
2.Or 4 , whichever is greater.
3.Accuracy is referred to reported impedance.
DS1073F1
15