CS43130 Datasheet, PDF (29/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.3 Class H Amplifier Output
Table 4-2 shows the nominal signal and volume level ranges when the output is set to the adapt modes explained in
Section 4.3.1. If the signal level is greater than the maximum value of this range, then clipping can occur.
Table 4-2. Class H Supply Modes
Mode
0
1
Class H Supply Level
±VP_LDO V, internally regulated from VP
±VCP
Signal ¹ or Volume Level Range ^2,3,4
 –11 dB
< –11 dB
1.In adapt-to-signal, the volume level ranges are approximations but are within –0.5 dB from the values shown.
2.Relative to digital full scale with output gain set to 0 dB.
3.In fixed modes, clipping can occur if the signal level exceeds the maximum of this range due to setting the
amplifier’s supply too low.
4.Thresholds shown are nominal for a 16-Ω stereo load.
4.3.1 Power Supply Control Options
This section describes the two types of operation: standard Class AB and adapt-to-output signal. The set of rail voltages
supplied to the amplifier output stages depends on the ADPT_PWR (see p. 112) setting.
4.3.1.1 Standard Class AB Operation (ADPT_PWR = 001 or 010)
If ADPT_PWR is set to 001 or 010, the rail voltages supplied to the amplifiers are held to ±VP_LDO or ±VCP, respectively.
The rail voltages supplied to the output stages are held constant, regardless of the output signal level. The CS43130
amplifiers simply operate in a traditional Class AB configuration.
4.3.1.2 Adapt-to-Output Signal (ADPT_PWR = 111)
If ADPT_PWR is set to 111, the rail voltage sent to the amplifiers is based solely on whether the signal sent to the amplifiers
would cause the amplifiers to clip when operating on the lower set of rail voltages at certain threshold values.
• If it would cause clipping, the control logic instructs the charge pump to provide the next higher set of rail voltages
to the amplifiers.
• If it would not cause clipping, the control logic instructs the charge pump to provide the lower set of rail voltages to
the amplifiers, eliminating the need to advise the CS43130 of volume settings external to the device.
4.3.2 Power-Supply Transitions
Charge-pump transitions from the lower to the higher set of rail voltages occur on the next FLYN/FLYP clock cycle. Despite
the system’s fast response time, the VCP_FILT pin’s capacitive elements prevent rail voltages from changing instantly.
Instead, the rail voltages ramp up from the lower to the higher supply, based on the time constant created by the output
impedance of the charge pump and the capacitor on the VCP_FILT pin (the transition time is approximately 20 µs).
Fig. 4-4 shows Class H supply switching. During this charging transition, a high dv/dt transient on the inputs may briefly
clip the outputs before the rail voltages charge to the full higher supply level. This transitory clipping has been found to be
inaudible in listening tests.
+VP_LDO
+VCP
Ideal Transition
Actual Transition caused
by VCP_FILT+ Capacitor
Time
-VCP
-VP_LDO
Figure 4-4. VCP_FILT Transitions
DS1073F1
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