CS43130 Datasheet, PDF (76/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
5.10.7 Switching MCLK Frequency
Ex. 5-17 shows steps necessary to switch the MCLK frequency in order to play audio at a different sample rate that is no
longer an integer divide of current MCLK. It makes the following assumptions:
• The CS43130 is already powered up and out of reset.
• MCLK is sourced directly from external clock input (Direct MCLK). MCLK_INT is 22.5792 MHz, and the sample rate
is an integer divide of MCLK.
• ASP is used for audio delivery and PDN_HP = 0.
Example 5-17. Sequence for Switching MCLK Frequency
STEP
TASK
1 Power down PCM
REGISTER/BIT FIELDS
VALUE
Refer to Ex. 5-5 for PCM power-down sequence
DESCRIPTION
2 Switch MCLK Source to RCO
3 Set MCLK Source to RCO
System Clocking Control 1. 0x10006
0x06
Reserved
MCLK_INT
MCLK_SRC_SEL
0000 0
1
10
Frequency of MCLK_INT is don't care
MCLK source set to RCO
4 Wait for 150 µs
5 Switch to a different MCLK Frequency. Assuming new MCLK frequency is 24.576MHz.
6 Change MCLK_INT frequency to
24.576 MHz
System Clocking Control 1. 0x10006
Reserved
MCLK_INT
MCLK_SRC_SEL
0x02
0000 0
0
10
MCLK_INT frequency set to 24.576 MHz
7 Apply PCM power-up initialization in Ex. 5-7
8 Configure ASP for appropriate sample rate, bit size and clock mode. Unmute PCM CHA and CHB outputs. Enable appropriate interrupts
9 Switch MCLK source to direct MCLK mode System Clocking Control 1. 0x10006
0x0
Reserved
MCLK_INT
MCLK_SRC_SEL
0000 0
0
00
MCLK_INT frequency set to 24.576 MHz
MCLK source set to direct MCLK mode
10 Wait at least 150 µs.
11 Power up HP
Refer to Ex. 5-9 for PCM power-up sequence. Skip Step 1 of Ex. 5-9 (completed in Step 7 above).
5.10.8 Headphone Detection
Ex. 5-18 shows steps necessary to detect the presence of a headphone. It makes the following assumptions:
• The CS43130 is already powered up and out of reset.
• The HP Detect register is not configured.
Example 5-18. Sequence for Headphone Detection
STEP
1
2
3
4
5
TASK
REGISTER/BIT FIELDS
Read Interrupt Status 1 register (0xF0000) to clear any sticky bits.
Read HP Status register (0xD0001) to clear any sticky bits.
Enable HPDETECT interrupts
Interrupt Mask 1. 0xF0010
Configure HP Detect parameters
Enable HP Detect
DAC_OVFL_INT_MASK
HPDETECT_PLUG_INT_MASK
HPDETECT_UNPLUG_INT_MASK
XTAL_READY_INT_MASK
XTAL_ERROR_INT_MASK
PLL_READY_INT_MASK
PLL_ERROR_INT_MASK
PDN_DONE_INT_MASK
HP Detect. 0xD0000
HPDETECT_CTRL
HPDETECT_INV
HPDETECT_RISE_DBC_TIME
HPDETECT_FALL_DBC_TIME
Reserved
HP Detect. 0xD0000
HPDETECT_CTRL
HPDETECT_INV
HPDETECT_RISE_DBC_TIME
HPDETECT_FALL_DBC_TIME
Reserved
VALUE
DESCRIPTION
data (0xF0010)
AND 0x9F
x
0
Enable HPDETECT interrupts
0
x
x
x
x
x
0x04
00
0
00
Rising edge debounce time set to 0 ms
10
Falling edge debounce time set to 500 ms
0
data (0xD0000)
OR (0xC0)
11
Enable headphone detection
x
xx
xx
0
76
DS1073F1