CS43130 Datasheet, PDF (50/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.10 DSD Interface
Each sample is 24 bits, as shown in Fig. 4-28, where the 8 most significant bits are used for the DSD marker and alternate
with each sample between 0x05/0xFA. Each channel within a sample contains the same marker. The remaining 16 least
significant bits are then used for the DSD data, with the first or oldest bit in Slot t0. It is required that markers are provided
continuously when the DoP interface is enabled, or a random sustained DC voltage asserts on loads from CS43130
outputs.
DSD Marker (8 MSB)
16 DSD Audio bits for one channel (oldest bit = t0)
dm7 dm6 dm5 dm4 dm3 dm2 dm1 dm0 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15
MSB
24-Bit PCM Frame
LSB
DoP Data Sample
LRCK (I²S)
SDATA
(DoP)
0x05
0x05
0xFA
0xFA
0x05
Data Stream Example of Stereo DoP
Figure 4-28. DoP Data Sample and Stereo Stream Example
Each PCM frame is assigned to a specific channel (left or right), and when used for DSD streaming, each PCM frame
contains only DSD data corresponding to its assigned channel. The CS43130 unpacks the received DoP data and reforms
it into a DSD stream to feed the internal DSD data paths.
It includes the following features:
• 24 bits per PCM data sample
• I²S format is supported
• DoP data is unpacked internally for DSD playback
• Clock Master and Slave Mode
• Up to 128 • Fs DSD stream
— Accepts a 64•Fs DSD stream with LRCK@176.4 kHz
— Accepts a 128•Fs DSD stream with LRCK@352.8 kHz
To enable DoP interface on the ASP to take in DSD source:
1. Configure the ASP per clocking/format required by DoP content.
2. Configure DSD_SPEED per DoP content.
3. Set DSD_PRC_SRC = 01 and DSD_EN = 1.
4.10 DSD Interface
The DSD interface is enabled or disabled by PDN_DSDIF bit. When cleared, the DSD data interface is enabled. When
using this interface, the DSD interface clock can be mastered by the CS43130 (DSD_M/SB=1). If set to Master Mode,
DSDCLK toggles if both PDN_DSDIF and XSP_3ST bits are cleared, and DSD_EN is set.
If the DSD interface clock is slaved (DSD_M/SB=0), when MCLK_INT is set as 22.5792 MHz, DSDCLK is required to be
synchronous to MCLK_INT. The DSDCLK can be derived by either:
• Exporting 1/4 or 1/8 the frequency of the CS43130 crystal to CLKOUT, or
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