CS43130 Datasheet, PDF (54/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.13 Control Port Operation
The control port operates using a I²C interface with the CS43130 acting as a slave device. Device communication must
not begin until t_PUD (refer to Table 3-20) after power conditions are ready and RESET is released.
4.13.1 I²C Control Port Operation
The I²C control port operates completely asynchronously with the audio sample rates. However, to avoid interference
problems, the I²C control-port pins must remain static if no operation is required.
The control-port uses the I²C interface, with the chip acting as a slave device. The I²C control port can operate in the
following modes:
• Standard Mode (SM), with a bit rate of up to 100 kbit/s
• Fast Mode (FM), with a bit rate of up to 400 kbit/s
• Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s
SDA is a bidirectional data line. Data is clocked into and out of the CS43130 by the SCL clock. Fig. 4-32, Fig. 4-33, and
Fig. 4-34 show signal timings for read and write cycles. A Start condition is defined as a falling transition of SDA while SCL
is high. A stop condition is defined as a rising transition of SDA while SCL is high. All other transitions of SDA must occur
while SCL is low.
To configure the last two bits of I²C address, CS43130 detects the ADR resistor connection type and measures the
resistance upon a device power up (POR event) or after a hardware reset event (RESET deasserted). Based on the
detected resistance, the I²C address is latched and cannot be changed until the next hardware reset event. The I²C
address configuration is not ready until t_PUD after the hardware reset event. During this period, the CS43130 does not
respond to any user-issued I²C command. After configuration, the IC tristates the ADR pin and becomes high impedance
internally to avoid a constant bias current.
When the ADR pin is directly connected to ground, the last two bits of the I²C address are configured as 00 (default). For
the other options, use a resistor (with 5% accuracy) as suggested in the Table 4-12.
Table 4-12. I²C Address Configurations
Connection Type
Pull-up to VL
Pull-up to VL
Pull-down to GND
Pull-down to GND
Resistor Value ()
0
4990
4990
0
Last Two Bits of I²C Address
11
10
01
00 (Default)
If the operation is a write, the 3 bytes after the chip address are the memory address pointer (MAP) that select the address
of the register to be read or written to next. The byte following the MAP is the control byte. Bit[0] of the control byte, INCR,
selects whether autoincrementing is to be used (INCR = 1), allowing successive reads or writes of consecutive registers.
Bits[2:1] of the control byte indicate the size of the data for the autoincrement to be acted on. Table 4-13 explains the
format for the I²C control byte.
Table 4-13. I²C Control-Byte Format
Bit Name
Description
7:3
— Reserved
Default: 0
2:1 SIZE Register access width. Specifies the width of the register access.
00 8-bit (1 byte)
01–11 Reserved
0
INCR Setting this bit allows the MAP address to autoincrement. The MAP address automatically increments every SIZE + 1 bytes
accessed consecutively.
0 Disabled
1 Enabled
Each byte transferred on the I²C bus is separated by an acknowledge (ACK) bit. The CS43130 acknowledges each input
byte read from the host, and the host must acknowledge each byte transmitted from the CS43130.
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