CS43130 Datasheet, PDF (40/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

4.7.2 Fractional-N PLL Internal Interface
Fig. 4-18 shows how PLL operation can be configured.
PDN_PLL p. 97
PLL_START p. 98
CS43130
4.7 Clock Output and Fractional-N PLL
XTI/MCLK
PLL_REF_
PREDIV
p. 99
PLL
PLL_OUT_
DIV p. 99
PLL_OUT
PLL_DIV_INT p. 98
PLL_DIV_FRAC_0 p. 98
PLL_DIV_FRAC_1 p. 98
PLL_DIV_FRAC_2 p. 98
PLL_MODE p. 99
Figure 4-18. Fractional-N PLL
Use Eq. 4-1 to calculate the PLL output frequency.
PLL_OUT =
PLL_REF
PLL_REF_PREDIV
×
PLL_DIV_INT + PLL_DIV_FRAC
500
512
or
1,
selected
by
PLL_Mode
×
1
PLL_OUT_DIV
Equation 4-1. PLL Output Frequency Equation
PLL_REF source must be in range below:
PLL_REF Source
MCLK/XIN pin
PLL_REF_PREDIV Input
Minimum
Maximum
9.6 MHz
26 MHz
Table 4-4 lists common settings with XTAL input as PLL reference.
Table 4-4. PLL Configuration for Typical Use Case (XTAL as the PLL Reference)
XTAL
(MHz)
22.5792
24.576
PLL_REF_PREDIV PLL_REF_PREDIV
(Divide-by Value)
(Setting)
PLL_
DIV_INT
PLL_DIV_FRAC
PLL_OUT_DIV
8
0x3
0x44
0x06 F700
0x08
8
0x3
0x49
0x80 0000
0x0A
PLL_
MODE
0
1
PLL
OUT
(MHz)
24.576
22.5792
PLL_CAL_
RATIO
139
118
Table 4-5 lists common settings with MCLK input as PLL reference.
Table 4-5. PLL Configuration for Typical Use Case (XIN/MCLK as the PLL Reference)
XIN/MCLK
(MHz)
PLL_REF_PREDIV
(Divide-by Value)
PLL_REF_PREDIV
(Setting)
PLL_DIV_INT
PLL_DIV_FRAC
PLL_OUT_DIV
11.2896
4
0x2
0x40
0x00 0000
0x08
4
0x2
0x44
0x06 F700
0x08
22.5792
8
0x3
0x44
0x06 F700
0x08
12.000
4
0x2
0x49
0x80 0000
0x0A
4
0x2
0x40
0x00 0000
0x08
24.000
8
0x3
0x49
0x80 0000
0x0A
8
0x3
0x40
0x00 0000
0x08
12.288
4
0x2
0x49
0x80 0000
0x0A
4
0x2
0x40
0x00 0000
0x08
24.576
8
0x3
0x49
0x80 0000
0x0A
9.600
4
0x2
0x49
0x80 0000
0x08
4
0x2
0x50
0x00 0000
0x08
PLL_
MODE
1
0
0
0
0
0
0
1
1
1
0
0
PLL_OUT PLL_CAL_
(MHz)
RATIO
22.5792
128
24.576
139
24.576
139
22.5792
120
24.576
131
22.5792
120
24.576
131
22.5792
118
24.576
128
22.5792
118
22.5792
151
24.576
164
40
DS1073F1