CS43130 Datasheet, PDF (102/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
7.3 ASP and XSP Registers
7.3.10
R/W
Default
ASP Clock Configuration
7
6
5
—
0
0
0
4
ASP_M/SB
0
Address 0x40018
3
ASP_SCPOL_
OUT
1
2
ASP_SCPOL_
IN
1
1
ASP_LCPOL_
OUT
0
0
ASP_LCPOL_
IN
0
Bits
Name
7:5
—
Reserved
4 ASP_M/SB ASP port master or slave configuration.
0 (Default) Slave Mode (input)
1 Master Mode (output)
3 ASP_SCPOL_ ASP SCLK output drive polarity.
OUT
0 Normal
1 (Default) Inverted
2 ASP_SCPOL_ ASP SCLK input polarity (pad to logic).
IN
0 Normal
1 (Default) Inverted
1 ASP_LCPOL_ ASP LRCK output drive polarity.
OUT
0 (Default) Normal
1 Inverted
0 ASP_LCPOL_ ASP LRCK input polarity (pad to logic).
IN
0 (Default) Normal
1 Inverted
Description
7.3.11 ASP Frame Configuration
Address 0x40019
R/W
7
6
5
4
3
2
1
0
—
ASP_STP
ASP_5050
ASP_FSD
Default
0
0
0
0
1
0
1
0
Bits
Name
Description
7:5
—
Reserved
4 ASP_STP ASP start phase. Controls which LRCK/FSYNC phase starts a frame.
0 (Default) The frame begins when LRCK/FSYNC transitions from high to low
1 The frame begins when LRCK/FSYNC transitions from low to high
3 ASP_5050 ASP LRCK fixed 50/50 duty cycle.
0 Programmable duty cycle per ASP_LCHI and ASP_LCPR.
1 (Default) Fixed 50% duty cycle
2:0 ASP_FSD ASP frame start delay (units of ASP_SCLK periods).
000 0 delay
001 0.5 delay
010 (Default) 1.0 delay
...
101 2.5 delay
110–111 Reserved
7.3.12 XSP Numerator 1
Address 0x40020
R/W
7
6
5
4
3
2
1
0
XSP_N_LSB
Default
0
0
0
0
0
0
0
1
Bits
Name
Description
7:0 XSP_N_LSB The value in this register cannot be changed while the serial port is powered up.
XSP sample rate fractional divide numerator LSB. Along with XSP_M_MSB/LSB, selects the fractional divide value for
setting the SCLK frequency.
(Default) XSP_N = 1
102
DS1073F1