CS43130 Datasheet, PDF (47/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.9 Audio Serial Port (ASP)
Table 4-7. Serial Port Clock Generation—Supported Configurations for 32-bits and 4 Channels
Frequency (MHz)
22.5792
24.576
LRCK/FSYNC
Rate (kHz)
SCLKs per LRCK Frame
xSP_LCPR + 1 xSP_LCPR[10:0]
xSP_N[15:0]
xSP_M[15:0]
32.000
128
127
80
441
44.100
128
127
1
4
48.000
128
127
40
147
88.200
128
127
1
2
96.000
128
127
80
147
176.400
128
127
1
1
32.000
128
127
1
6
44.100
128
127
147
640
48.000
128
127
1
4
88.200
128
127
147
320
96.000
128
127
1
2
176.400
128
127
147
160
192.000
128
127
1
1
4.9.6 Channel Location and Size
Each serial-port channel has a programmable location offset (xSP_RX_CHn). Channel location is programmable in single
SCLK period resolution. When set to the minimum location offset, the channel transmits or receives on the first SCLK
period of a new frame.
Channel size is programmable in byte resolution from 8 to 32 bits using xSP_RX_CHn_RES. Channel size and location
must not be programmed such that channel data extends beyond the frame boundary. Size and location must not be
programmed such that data from a given SCLK period is assigned to more than one channel. The example in Fig. 4-25
shows channel location and size.
First SCLK latching edge of a
new frame after frame sync
0
SCLK
7
N
7
Traditional
‘Slot’
Slot 0
07
Slot 1
Channel Location (xSP_RX_CHn) = N
247
248
255
07
0
Slot 30
Slot 31
Channel Size
= 11
TDM
Channel M Data
Channel Size
= 10
Channel Size
= 01
Channel Size
= 00
31 _{Ch. M MSB}
23 _{Ch. M MSB}
15 _{Ch. M MSB}
7 _{Ch. M MSB} 0
Ch. M LSB ⁰
Ch. M LSB ⁰
Ch. M LSB ⁰
Don’t Care
Don’t Care
Don’t Care
Figure 4-25. Example Channel Location and Size
4.9.7 Frame Start Phase
The serial port can start a frame when xSP_LRCK/FSYNC is high or low, depending on xSP_STP. In typical TDM use
cases, a frame starts when FSYNC is high (xSP_STP = 1).
DS1073F1
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