CS43130 Datasheet, PDF (19/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
3 Characteristics and Specifications
Table 3-11. Digital Interface Specifications and Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43130 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground;
parameters can vary with VL and VP; typical performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; min/max performance
data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; T_A = +25°C; C_L = 60 pF.
Parameters ¹
Symbol
Input leakage current ^2,3
LRCK1, DSDB/LRCK2
I_in
SDIN1, SCLK1, DSDA/SDIN2, DSDCLK/SCLK2
HP_DETECT
SDA, SCL
INT, RESET
Internal weak pull-down
—
Input capacitance
—
INT current sink (V_OL = 0.3 V maximum)
VL Logic (non-I²C)
VL Logic (I²C only)
HP_DETECT ⁴
HP_DETECT current to VCP_FILT– ⁴
—
High-level output voltage (I_OH = –100 µA)
V_OH
Low-level output voltage
V_OL
High-level input voltage
V_IH
Low-level input voltage
V_IL
Hysteresis voltage (Fast Mode and Fast Mode Plus)
Low-level output voltage
High-level input voltage
Low-level input voltage
V_HYS
V_OL
V_IH
V_IL
High-level input voltage
V_IH
Low-level input voltage
V_IL
I_{HP_DETECT}
Minimum Maximum Units
—
±4
µA
—
±3
µA
—
±100 nA
—
±100 nA
—
±100 nA
550
2450 k
—
10
pF
825
—
µA
0.9•VL
—
V
—
0.1•VL V
0.7•VL
—
V
—
0.3•VL V
0.05•VL
—
V
—
0.2•VL V
0.7•VL
—
V
—
0.3•VL V
0.93•VP
—
V
—
2.0
V
1.00
2.91
µA
1.See Table 1-1 for serial and control-port power rails.
2.Specification is per pin.
3.Includes current through internal pull-up or pull-down resistors on pin.
4.The HP_DETECT input circuit allows the HP_DETECT signal to be as low of a voltage as VCP_FILT– and as high as VP. Section 4.5.1 provides
configuration details.
Table 3-12. CLKOUT Characteristics
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; C_L = 60 pF; PLL reference input must meet the phase-noise mask specified in Fig. 4-15; TA = +25°C; Output jitter is measured from 100 Hz
to half of the output frequency.
CLKOUT output frequency
Parameters
CLKOUT output duty cycle
CLKOUT output TIE jitter (RMS)
CLKOUT_SRC_SEL = 01
Symbol
f_CLKOUT
—
t_JIT
Minimum
2.8224
5.6448
7.5264
11.2896
40
—
Typical
3
6
8
12
50
500
Maximum Units
3.072
6.144
8.192
12.288
MHz
MHz
MHz
MHz
60
%
—
ps
Table 3-13. PLL Characteristics
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; PLL reference input must meet the phase-noise mask specified in Fig. 4-15; TA = +25°C.
PLL output frequency
PLL lock time
PLL reference clock input
Parameters
PLL reference clock input jitter
Symbol
f_out
t_Lock
—
—
Minimum
22.5792
—
—
—
—
—
—
—
—
—
—
—
—
Typical
24
620
11.2896
22.5792
12.2880
24.5760
9.6000
19.2000
12.0000
24.0000
13.0000
26.000
—
Maximum Units
24.576 MHz
1000
µs
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
50
ps
DS1073F1
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