CS43130 Datasheet, PDF (78/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
Example 5-19. DoP and PCM Mixing (Cont.)
STEP
TASK
16 Configure XSP Frame
17 Set XSP Channel Location
18 Set XSP Channel Size and
Enable
19 Configure DSD Processor
20 Configure DSD Volume
21 Configure DSD path Signal
Control 1
REGISTER/BIT FIELDS
XSP Frame Configuration. 0x40029
Reserved
XSP_STP
XSP_5050
XSP_FSD
XSP Channel 1 Location. 0x60000
XSP_RX_CH1
XSP Channel 2 Location. 0x60001
XSP_RX_CH2
XSP Channel 1 Size and Enable.
0x6000A
Reserved
XSP_RX_CH1_AP
XSP_RX_CH1_EN
XSP_RX_CH1_RES
XSP Channel 2 Size and Enable.
0x6000B
Reserved
XSP_RX_CH2_AP
XSP_RX_CH2_EN
XSP_RX_CH2_RES
DSD Volume A. 0x70001
DSD_VOLUME_A
DSD Processor Path Signal Control 1.
0x70002
Reserved
DSD_VOL_BEQA
DSD_SZC
Reserved
DSD_AMUTE
DSD_AMUTE_BEQA
DSD_MUTE_A
DSD_MUTE_B
22 Configure DSD Interface
DSD Interface Configuration.
0x70003
Reserved
DSD_M/SB
DSD_PM_EN
DSD_PM_SEL
23 Configure DSD path Signal DSD Processor Path Signal Control 2.
Control 2
0x70004
Reserved
DSD_PRC_SRC
DSD_EN
Reserved
DSD_SPEED
STA_DSD_DET
INV_DSD_DET
24 Configure DSD path Signal DSD Processor Path Signal Control 3.
Control 3
0x70006
DSD_ZERODB
DSD_HPF_EN
Reserved
SIGCTL_DSDEQPCM
DSD_INV_A
DSD_INV_B
DSD_SWAP_CHAN
DSD_COPY_CHAN
25 Configure HP Output for 1.732 Vrms
26 Configure Class H
Amplifier
Class H Control. 0xB0000
Reserved
ADPT_PWR
HV_EN
EXT_VCPFILT
27 Set HP output to full
scale
HP Output Control 1. 0x80000
Reserved
OUT_FS
Reserved
VALUE
0x0A
000
0
1
010
0x00
0x00
0x00
0x00
0x06
DESCRIPTION
Configure XSP port to accept I²S input
XSP Channel 1 starts on SCLK0
XSP Channel 2 starts on SCLK0
0000
0
1
10
0x0E
XSP Channel 1 Active Phase
XSP Channel 1 Enable
XSP Channel 1 Size is 24 bits
0000
1
1
10
XSP Channel 2 Active Phase
XSP Channel 2 Enable
XSP Channel 2 Size is 24 bits
0x00
0x00
0xEC
Channel A volume set to 0 dB
1
1
1
0
1
1
0
0
0x00
DSD Volume B equals DSD volume A
Soft ramp control enabled
Mute occurs after 256 repeated 8-bit DSD mute patterns
Mute happens only when mute pattern is detected in both
channels
Function is disabled
Function is disabled
0000 0
0 DSD_M/SB is don’t care
0 Function is disabled
0 Function is disabled
0x70
0
11
1
0
0
0
0
0xC0
Set source of DSD processor to XSP
Enable DSD playback
Set DSD clock speed to 64•FS
Static DSD detection disabled
Invalid DSD detection disabled
1 DSD stream volume setting
1 Enable DSD HPF
0
0 Function is disabled
0 Function is disabled
0 Function is disabled
0 Function is disabled
0 Function is disabled
0x1E
000
111
1
0
0x30
00
11
0000
Output Signal determines voltage level
High Voltage Mode enabled
Using Internal VCPFILT source.
Set HP output to Full Scale (1.732 Vrms)
78
DS1073F1