CS43130 Datasheet, PDF (69/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
5.10.3 Power-Up Sequence to DoP Playback with PLL
In Ex. 5-13, an external 19.2-MHz MCLK is used with a PLL to generate an internal MCLK or 22.5792 MHz, and the ASP
is in clock master receiving DoP data with LRCLK at 176.4 kHz and SCLK at 8.4672 MHz.
Example 5-13. DoP Playback with PLL
STEP
TASK
REGISTER/BIT FIELDS
1 _{Apply all relevant power supplies, then assert RESET.}
VALUE
DESCRIPTION
2 Wait for 1.5 ms
3 Apply DSD power-up initialization in Ex. 5-8
4 Configure PLL. XTI/MCLK input coming from an external 19.2 MHz source with PLL output set to 22.5792 MHz. Refer to Section 4.7.2 for register
settings for other frequency combinations
5 Power up PLL
Power Down Control. 0x20000
0xFA
PDN_XSP
PDN_ASP
PDN_DSDIF
PDN_HP
PDN_XTAL
PDN_PLL
PDN_CLKOUT
Reserved
x
x
x
x
x
0 Power up PLL block
x
0
6 Set PLL Predivide value
PLL Setting 9. 0x40002
0x03
Reserved
PLL_REF_PREDIV
0000 00
11 Set PLL predivide value to 8
7 Set PLL output divide
PLL Setting 6. 0x30008
0x08
PLL_OUT_DIV
0x08 Set PLL output divide value to 8
8 Set Fractional portion of PLL Divide Ratio
PLL Setting 2. 0x30002
0x00
PLL_DIV_FRAC_0
0x00 Set LSB of PLL fractional divider value to 0
PLL Setting 3. 0x30003
0x00
PLL_DIV_FRAC_1
0x00 Set Middle Byte of PLL fractional divider value to 0
PLL Setting 4. 0x30004
0x80
PLL_DIV_FRAC_2
0x80 Set MSB of PLL fractional divider value to 0x80
9 Set Integer portion of PLL Divide Ratio
PLL Setting 5. 0x30005
0x49
PLL_DIV_INT
0x49 Set PLL integer Divide value to 0x49
10 Set PLL mode
PLL Setting 8. 0x3001B
0x01
Reserved
PLL_MODE
Reserved
0000 00
0 500/512 factor is used in PLL frequency calculation
1
11 Read Interrupt Status 1 register (0xF0000) to clear sticky bits.
12 Set PLL calibration ratio
PLL Setting 7. 0x3000A
0x97
PLL_CAL_RATIO
0x97 PLL Calibration Ratio is set to 0x97 (151)
13 Enable PLL interrupts
Interrupt Mask 1. 0xF0010
0xF9
DAC_OVFL_INT_MASK
1 DAC_OVFL_INT is don't care
HPDETECT_PLUG_INT_MASK
1 Unmask HPDETECT_PLUG interrupt
HPDETECT_UNPLUG_INT_MASK 1 Unmask HPDETECT_UNPLUG interrupt
XTAL_READY_INT_MASK
1 XTAL_READY_INT is Don't Care
XTAL_ERROR_INT_MASK
1 XTAL_ERROR_INT is Don't Care
PLL_READY_INT_MASK
0 PLL_READY Interrupt is already unmasked
PLL_ERROR_INT_MASK
0 PLL_ERROR Interrupt is already unmasked
PDN_DONE_INT_MASK
1 PDN_DONE_INT is Don't Care
14 Start PLL
PLL Setting 1. 0x30001
0x01
Reserved
PLL_START
15 Playback DoP audio. Assuming 64•Fs DSD stream
0000 000
1 Enable PLL Output
16 Configure ASP interface for DoP input
17 Set ASP sample rate
Serial Port Sample Rate. 0x1000B 0x05
Reserved
ASP_SPRATE
0000
0101 Set sample rate to 176.4 kHz
18 Set ASP sample bit size. XSP is don't care Serial Port Sample Bit Size. 0x1000C 0x05
Reserved
XSP_SPSIZE
ASP_SPSIZE
0000
01 XSP sample bit size set to 24 bits
01 ASP sample bit size set to 24 bits
DS1073F1
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