CS43130 Datasheet, PDF (71/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
5.10 Example Sequences
Example 5-13. DoP Playback with PLL (Cont.)
STEP
TASK
31 Configure DSD interface
REGISTER/BIT FIELDS
DSD Interface Configuration.
0x70003
VALUE
0x04
DESCRIPTION
Reserved
DSD_M/SB
DSD_PM_EN
DSD_PM_SEL
0000 0
1 DSD is clock master
0 Function is disabled
0 Function is disabled
32 Configure DSD Path Signal Control 2
DSD Processor Path Signal Control 2. 0x50
0x70004
Reserved
DSD_PRC_SRC
DSD_EN
Reserved
DSD_SPEED
STA_DSD_DET
INV_DSD_DET
0
10 Set source of DSD processor to ASP
1 Enable DSD playback
0
0 Set DSD clock speed to 64•Fs
0 Static DSD detection disabled
0 Invalid DSD detection disabled
33 Configure DSD path Signal Control 3
DSD Processor Path Signal Control 3. 0xC0
0x70006
DSD_ZERODB
DSD_HPF_EN
Reserved
SIGCTL_DSDEQPCM
DSD_INV_A
DSD_INV_B
DSD_SWAP_CHAN
DSD_COPY_CHAN
1 The SACD 0–dB reference level (50%modulation
index) matches PCM 0-dB full scale.
1 Enable HPF in DSD processor
0
0 Function is disabled
0 Function is disabled
0 Function is disabled
0 Function is disabled
0 Function is disabled
34 Configure headphone output for 1.732 V rms
35 Configure Class H amplifier
Class H Control. 0xB0000
0x1E
Reserved
ADPT_PWR
HV_EN
EXT_VCPFILT
000
1 11 Output signal determines voltage level
1 High voltage mode enabled
0 Using internal VCPFILT source.
36 Set HP output to full scale
HP Output Control 1. 0x80000
0x30
HP_CLAMPA
HP_CLAMPB
OUT_FS
HP_IN_EN
Reserved
0
0
11 Set headphone output to full scale (1.732 V rms)
0
000
37 Headphone detect
HP Detect. 0xD0000
0xC4
HPDETECT_CTRL
HPDETECT_INV
HPDETECT_RISE_DBC_TIME
HPDETECT_FALL_DBC_TIME
Reserved
11 HP detect enabled
0 HP detect input is not inverted
0 0 Tip Sense rising debounce time set to 0 ms
10 Tip sense falling debounce time set to 500 ms
0
38 Enable interrupts
39 Read Interrupt Status 1 register (0xF0000), Interrupt Status 2 register (0xF0001) and Interrupt Status 5 register (0xF0004) to clear sticky bits.
40 Enable headphone detect interrupts
Interrupt Mask 1. 0xF0010
0x99
DAC_OVFL_INT_MASK
1 DAC_OVFL_INT is don't care
HPDETECT_PLUG_INT_MASK
0 Enable HPDETECT_PLUG interrupt
HPDETECT_UNPLUG_INT_MASK 0 Enable HPDETECT_UNPLUG interrupt
XTAL_READY_INT_MASK
1 XTAL_READY_INT is don't care
XTAL_ERROR_INT_MASK
1 XTAL_ERROR_INT is don't care
PLL_READY_INT_MASK
0 PLL_READY interrupt already enabled
PLL_ERROR_INT_MASK
0 PLL_ERROR interrupt already enabled
PDN_DONE_INT_MASK
1 PDN_DONE_INT is don't care
41 Enable ASP interrupts
Interrupt Mask 2. 0xF0011
0x07
ASP_OVFL_INT_MASK
ASP_ERROR_INT_MASK
ASP_LATE_INT_MASK
ASP_EARLY_INT_MASK
ASP_NOLRCK_INT_MASK
Reserved
0 Enable ASP_OVFL interrupt
0 Enable ASP_ERROR interrupt
0 Enable ASP_LATE interrupt
0 Enable ASP_EARLY interrupt
0 Enable ASP_NOLRCK interrupt
111
42 Enable DSD and DoP interrupts
Interrupt Mask 5. 0xF0014
0x01
DSD_STUCK_INT_MASK
DSD_INVAL_A_INT_MASK
DSD_INVAL_B_INT_MASK
DSD_SILENCE_A_INT_MASK
DSD_SILENCE_B_INT_MASK
DSD_RATE_ERROR_INT_MASK
DOP_MRK_DET_INT_MASK
DOP_ON_INT_MASK
0 Enable DSD_STUCK interrupt
0 Enable DSD_INVAL_A interrupt
0 Enable DSD_INVAL_B interrupt
0 Enable DSD_SILENCE_A interrupt
0 Enable DSD_SILENCE_B interrupt
0 Enable DSD_RATE_ERROR interrupt
0 Enable DOP_MRK_DET interrupt
1 Disable DOP_ON interrupt
43 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000).
DS1073F1
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