CS43130 Datasheet, PDF (52/137 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver

CS43130
4.11 DSD and PCM Mixing
4.11 DSD and PCM Mixing
For mobile application, the CS43130 provides a feature for mixing in PCM notification during DSD playback, with the setup
in Table 4-10.
Table 4-10. Mixing Configurations Supported by the CS43130
PCM Input Configuration
I²S or TDM on
ASP
44.1 kHz
Master
Slave ¹
Master
Slave ¹
DSD on DSD IF
DoP on XSP
1.The ASP/XSP subclocks and DSDCLK are required to be synchronous.
DSD Input Configuration
2.8224 or 5.6448 MHz
on DSDCLK
176.4 or 352.8 kHz
Master
Slave ¹
Master
Slave ¹
It is assumed that the DSD path has been properly configured for DSD playback, and DSD_AMUTE function is disabled.
During normal DSD playback, the ASP can be shut down. At the PCM notification event, the ASP must be properly
configured to receive PCM samples at 44.1 kHz. After the ASP subclocks are running, set MIX_PCM_PREP to indicate to
the CS43130 that the PCM mixing event is imminent. After 1.6 ms, MIX_PCM_DSD can be safely set to initiate the mixing
process. After the PCM notification mixing is complete, clear both MIX_PCM_DSD and MIX_PCM_PREP at the same
time. If desired, the ASP can be shut down to save power.
When mixing, use both PCM and DSD volume controls to attenuate the signal content on both paths (e.g., at least –6-dB
attenuation on each) to avoid clipping on the mixing product. Use PCM_VOLUMEx to adjust the PCM path and DSD_
VOLUMEx to adjust the DSD path. All the signal path settings apply to both path’s individual settings.
PCM
DSD
PCM_VOLUME_B p. 110
PCM_VOLUME_A p. 110
Interpolation
ASP
Filter &
Volume
Control
Multibit


Modulator
XSP /
DSD Audio
Interface
DoP to
DSD
Engine
MIX_PCM_PREP p. 108
MIX_PCM_DSD p. 108
DSD
Processor
DSD_VOLUME_B p. 106
DSD_VOLUME_A p. 107
Figure 4-30. PCM and DSD Mixing Signal Flow
4.12 Standard Interrupts
The interrupt output pin, INT, is used to signal the occurrence of events within the device’s interrupt status registers. Events
can be masked individually by setting corresponding bits in the interrupt mask registers. Table 4-11 lists interrupt status
and mask registers. The configuration of mask bits determines which events cause the immediate assertion of INT:
• When an unmasked interrupt status event is detected, the status bit is set, and INT is asserted.
• When a masked interrupt status event is detected, the interrupt status bit is set, but INT is not affected.
Once INT is asserted, it remains asserted until all status bits that are unmasked and set have been read. Interrupt status
bits are sticky and read-to-clear. Once set, they remain set until the register is read and the associated interrupt condition
is not present. If a condition is still present and the status bit is read, although INT is deasserted, the status bit remains set.
To clear status bits set due to the initiation of a block, all interrupt status bits must be read after the corresponding module
is enabled and before normal operation begins. Otherwise, unmasking these previously set status bits causes assertion
of INT.
Interrupt source bits are set when edge-detect interrupts is detected, and they remain set until the register is read and the
condition that caused the bit to assert is no longer present.
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