EP2SGX30CF780C5N Datasheet, PDF (9/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

2. Stratix II GX Architecture
SIIGX51003-2.2
Transceivers
Stratix^® II GX devices incorporate dedicated embedded circuitry on the
right side of the device, which contains up to 20 high-speed 6.375-Gbps
serial transceiver channels. Each Stratix II GX transceiver block contains
four full-duplex channels and supporting logic to transmit and receive
high-speed serial data streams. The transceivers deliver bidirectional
point-to-point data transmissions, with up to 51 Gbps (6.375 Gbps per
channel) of full-duplex data transmission per transceiver block.
Figure 2–1 shows the function blocks that make up a transceiver channel
within the Stratix II GX device.
Figure 2–1. Stratix II GX Transceiver Block Diagram
PMA Analog Section
PCS Digital Section
n
Deserializer
(1)
Clock
Recovery
Unit
Word
Aligner
XAUI
Lane
Deskew
Rate
Matcher
Reference
Clock
Receiver
PLL
Reference
Clock
Transmitter
PLL
n
Serializer
(1)
8B/10B
Encoder
8B/10B
Decoder
Byte
Deserializer
Byte
Serializer
Byte
Ordering
FPGA Fabric
m
Phase
Compensation
FIFO Buffer
(2)
Phase
m
Compensation
FIFO Buffer
(2)
Notes to Figure 2–1:
(1) n represents the number of bits in each word that need to be serialized by the transmitter portion of the PMA or have
been deserialized by the receiver portion of the PMA. n = 8, 10, 16, or 20.
(2) m represents the number of bits in the word that pass between the FPGA logic and the PCS portion of the transceiver.
m = 8, 10, 16, 20, 32, or 40.
Transceivers within each block are independent and have their own set of
dividers. Therefore, each transceiver can operate at different frequencies.
Each block can select from two reference clocks to provide two clock
domains that each transceiver can select from.
Altera Corporation
2–1
October 2007