EP2SGX30CF780C5N Datasheet, PDF (300/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

PLL Timing
Specifications
Tables 4–110 and 4–111 describe the Stratix II GX PLL specifications when
operating in both the commercial junction temperature range (0 to 85 C)
and the industrial junction temperature range (–40 to 100 C), except for
the clock switchover and phase-shift stepping features. These two
features are only supported from the 0 to 100 C junction temperature
range.
Table 4–110. Enhanced PLL Specifications (Part 1 of 2)
Name
f_IN
f_INPFD
f_INDUTY
f_ENDUTY
t_INJITTER
t_OUTJITTER
t_FCOMP
f_OUT
f_OUTDUTY
f_SCANCLK
t_CONFIGEPLL
f_{OUT_EXT}
t_LOCK
t_DLOCK
f_SWITCHOVER
f_CLBW
Description
Min
Typ
Max
Unit
Input clock frequency
4
500
MHz
Input frequency to the PFD
4
420
MHz
Input clock duty cycle
40
60
%
External feedback input clock duty
40
cycle
Input or external feedback clock input
jitter tolerance in terms of period jitter.
Bandwidth ≤0.85 MHz
Input or external feedback clock input
jitter tolerance in terms of period jitter.
Bandwidth > 0.85 MHz
Dedicated clock output period jitter
External feedback compensation time
60
%
0.5
ns (peak-
to-peak)
1.0
ns (peak-
to-peak)
250 ps for ≥
100 MHz outclk
25 mUI for <
100 MHz outclk
ps or mUI
(p-p)
10
ns
Output frequency for internal global or 1.5 (2)
regional clock
Duty cycle for external clock output
45
50
550
MHz
55
%
Scanclk frequency
100
MHz
Time required to reconfigure scan
chains for EPLLs
174/f_SCANCLK
PLL external clock output frequency 1.5 (2)
(1)
ns
MHz
Time required for the PLL to lock from
0.03
the time it is enabled or the end of
device configuration
Time required for the PLL to lock
dynamically after automatic clock
switchover between two identical clock
frequencies
Frequency range where the clock
1.5
1
switchover performs properly
PLL closed-loop bandwidth
0.13
1.2
1
ms
1
ms
500
MHz
16.9
MHz