EP2SGX30CF780C5N Datasheet, PDF (218/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Operating Conditions
Table 4–31. PCML Specifications Note (1)
Symbol
Parameter
References
Reference Clock
3.3-V PCML
1.5-V PCML
1.2-V PCML
Reference clock supported
PCML standards
V_ID
Peak-to-peak differential input
voltage
V_ICM
R
Input common mode voltage
On-chip termination resistors
Receiver
3.3-V PCML
1.5-V PCML
1.2-V PCML
Receiver supported PCML
standards
V_ID
Peak-to-peak differential input
voltage
V_ICM
R
Input common mode voltage
On-chip termination resistors
Transmitter
1.5-V PCML Transmitter supported PCML
1.2-V PCML standards
V_CCH
V_OD
Output buffer supply voltage
Peak-to-peak differential output
voltage
The specifications are located in the Reference Clock section
of Table 4–6 on page 4–4.
The specifications listed in Table 4–6 are applicable to PCML
input standards.
The specifications are located in the Receiver section of
Table 4–6 on page 4–4.
The specifications listed in Table 4–6 are applicable to PCML
input standards.
The specifications are located in Table 4–5 on page 4–4.
The specifications are located in Tables 4–7, 4–8, 4–9, 4–10,
4–11, and 4–12.
V_OCM
R
Output common mode voltage
On-chip termination resistors
The specifications listed in these tables are applicable to
PCML output standards.
The specifications are located in the Transmitter section of
Table 4–6 on page 4–4.
The specifications listed in Table 4–6 are applicable to PCML
output standards.
Note to Table 4–31:
(1) Stratix II GX devices support PCML input and output on GXB banks 13, 14, 15, 16, and 17. This table references
Stratix II GX PCML specifications that are located in other sections of the Stratix II GX Device Handbook.
4–48
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009