EP2SGX30CF780C5N Datasheet, PDF (109/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–71. Global and Regional Clock Connections from Center Clock Pins and Fast PLL Outputs Notes (1),
(2)
CLK0
CLK1
C0
Fast C1
PLL 1
C2
C3
Logic Array
Signal Input
To Clock
Network
CLK2
CLK3
C0
Fast C1
PLL 2
C2
C3
RCLK0
RCLK2
RCLK4
RCLK6
GCLK0
GCLK2
RCLK1
RCLK3
RCLK5
RCLK7
GCLK1
GCLK3
Notes to Figure 2–71:
(1) EP2SGX30C/D and P2SGX60C/D devices only have two fast PLLs (1 and 2) and two Enhanced PLLs (5 and 6), but
the connectivity from these PLLs to the global and regional clock networks remains the same as shown.
(2) The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
Altera Corporation
October 2007
2–101
Stratix II GX Device Handbook, Volume 1