EP2SGX30CF780C5N Datasheet, PDF (41/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–26 shows the data path in reverse serial loopback mode.
Figure 2–26. Stratix II GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
FPGA
Logic
Array
TX Phase
Compensation
FIFO
BIST
Incremental
Verify
Byte
Serializer
RX Phase
Compen-
sation
FIFO
Byte
Ordering
8B/10B
20 ^Encoder
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
Analog Receiver and
Transmitter Logic
Serializer
BIST
PRBS
Verify
Deskew
FIFO
Word
Aligner
Reverse
Serial
Loopback
De-
serializer
Clock
Recovery
Unit
Receiver Digital Logic
Reverse Serial Pre-CDR Loopback
The reverse serial pre-CDR loopback mode uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, loops back before the CRU
unit, and is transmitted though the high-speed differential transmitter
output buffer. It is for test or verification use only to verify the signal
being received after the gain and equalization improvements of the input
buffer. The signal at the output is not exactly what is received since the
signal goes through the output buffer and the VOD is changed to the
VOD setting level. The pre-emphasis settings have no effect.
Altera Corporation
October 2007
2–33
Stratix II GX Device Handbook, Volume 1