EP2SGX30CF780C5N Datasheet, PDF (301/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Table 4–110. Enhanced PLL Specifications (Part 2 of 2)
Name
Description
Min
Typ
f_VCO
PLL VCO operating range for –3 and 300
–4 speed grade devices
PLL VCO operating range for –5 speed 300
grade devices
f_SS
Spread-spectrum modulation
100
frequency
% spread
Percent down spread for a given clock 0.4
0.5
frequency
t_{P L L _ P S E R R}
Accuracy of PLL phase shift
t_ARESET
Minimum pulse width on areset
10
signal.
t_{ARESET_RECONFIG} Minimum pulse width on the areset 500
signal when using PLL reconfiguration.
Reset the PLL after scandone goes
high.
t_RECONFIGWAIT
The time required for the wait after the
reconfiguration is done and the areset
is applied.
Max
1,040
840
500
0.6
±30
Unit
MHz
MHz
kHz
%
ps
ns
ns
2
us
(1) This is limited by the I/O f_MAX. See Tables 4–91 through 4–95 for the maximum.
(2) If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
Table 4–111. Fast PLL Specifications (Part 1 of 2)
Name
Description
Min
Typ
Max Unit
f_IN
f_INPFD
f_INDUTY
t_INJITTER
Input clock frequency (for -3 and -4 speed
16
grade devices)
Input clock frequency (for -5 speed grade
16
devices)
Input frequency to the PFD
16
Input clock duty cycle
40
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤2 MHz
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 0.2 MHz
717 MHz
640 MHz
500 MHz
60
%
0.5
ns (p-p)
1.0
ns (p-p)