EP2SGX30CF780C5N Datasheet, PDF (235/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

DC and Switching Characteristics
Table 4–54. Timing Measurement Methodology for Input Pins (Part 2 of 2) Notes (1), (2), (3), (4)
I/O Standard
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS
LVPECL
Measurement Conditions
Measurement Point
V_CCIO (V)
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
3.135
V_REF (V)
0.830
0.688
0.688
0.570
1.163
1.163
0.830
0.830
0.688
0.688
0.830
0.830
Edge Rate (ns)
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
0.100
0.100
VMEAS (V)
0.83
0.6875
0.6875
0.570
1.1625
1.1625
0.83
0.83
0.6875
0.6875
0.83
0.83
1.1625
1.5675
Notes to Table 4–54:
(1) Input buffer sees no load at buffer input.
(2) Input measuring point at buffer input is 0.5 V_CCIO.
(3) Output measuring point is 0.5 V_CC at internal node.
(4) Input edge rate is 1 V/ns.
(5) Less than 50-mV ripple on V_CCIO and V_CCPD, V_CCINT = 1.15 V with less than 30-mV ripple.
(6) V_CCPD = 2.97 V, less than 50-mV ripple on V_CCIO and V_CCPD, V_CCINT = 1.15 V.
Altera Corporation
June 2009
4–65
Stratix II GX Device Handbook, Volume 1