EP2SGX30CF780C5N Datasheet, PDF (77/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Table 2–18. Stratix II GX Device Routing Scheme (Part 2 of 2)
Destination
Source
Column IOE
Row IOE
v
vv
vvvv
TriMatrix
Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM. Although these memory blocks are different, they can all
implement various types of memory with or without parity, including
true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO
buffers. Table 2–19 shows the size and features of the different RAM
blocks.
Table 2–19. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
Maximum performance
True dual-port memory
Simple dual-port memory
Single-port memory
Shift register
ROM
FIFO buffer
Pack mode
Byte enable
Address clock enable
Parity bits
Mixed clock mode
Memory initialization (.mif)
M512 RAM Block
(32 × 18 Bits)
500 MHz
v
v
v
v
v
v
v
v
v
M4K RAM Block
(128 × 36 Bits)
550 MHz
v
v
v
v
v
v
v
v
v
v
v
v
M-RAM Block
(4K × 144 Bits)
420 MHz
v
v
v
(1)
v
v
v
v
v
v
Altera Corporation
October 2007
2–69
Stratix II GX Device Handbook, Volume 1